DS50EV401-EVK National Semiconductor, DS50EV401-EVK Datasheet - Page 3

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DS50EV401-EVK

Manufacturer Part Number
DS50EV401-EVK
Description
KIT EVAL DS50EV401 EQUALIZER
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of DS50EV401-EVK

Main Purpose
Interface, Cable Equalizer
Utilized Ic / Part
DS50EV401
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
POWER
V
GND
Exposed
Pad
OTHER
Reserv
Pin Name
DD
Note: I = Input O = Output
Connection Diagram
Ordering Information
NSID
DS50EV401SQ
DS50EV401SQE
DS50EV401SQX
Pin Number
16, 17, 18,
19, 20, 21,
23, 37, 47,
3, 6, 7,
10, 13,
22, 24,
27, 30,
15, 46
31, 34
DAP
48
I/O, Type
Ground
Ground
Power
Package
48 Lead LLP Package
48 Lead LLP Package
48 Lead LLP Package
V
path. A 0.1μF bypass capacitor should be connected between each V
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
Reserved. Do not connect. Leave open.
DD
= 2.5V ± 5% or 3.3V ± 10%. V
TOP VIEW — Not to scale
3
Tape & Rell QTY
DD
pins should be tied to V
1,000
2,500
Description
250
DD
plane through low inductance
30050526
Package Number
SQA48D
SQA48D
SQA48D
DD
pin to GND planes.
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