DS50EV401-EVK National Semiconductor, DS50EV401-EVK Datasheet - Page 9

• Manufacturer Part Number: DS50EV401-EVK
• Description: KIT EVAL DS50EV401 EQUALIZER
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50EV401-EVK

• Main Purpose: Interface, Cable Equalizer
• Utilized Ic / Part: DS50EV401
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Applications Information
GENERAL RECOMMENDATIONS
The DS50EV401 is a high performance device capable of
delivering excellent performance. As with most CML devices,
it is recommended that AC coupling capacitors be used to
ensure I/O compatibility with other devices. In order to extract
full performance from the device in a particular application,
good high-speed design practices must be followed. National
Semiconductor’s LVDS Owner's Manual, provides detailed
information about managing signal integrity and power deliv-
ery to get the most from your design.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs must have a controlled differen-
tial impedance of 100Ω. It is preferable to route CML lines
exclusively on one layer of the board, particularly for the input
traces. The use of vias should be avoided if possible. If vias
must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair.
Route the CML signals away from other signals and noise
sources on the printed circuit board. See AN-1187 for addi-
tional information on LLP packages.
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PACKAGE FOOTPRINT / SOLDERING
See National's Application Note number 1187, “Leadless
Leadframe Package” for information on PCB footprint and
soldering recommendations.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS50EV401 is provided with an adequate power supply.
First, the supply (V
nected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the V
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1μF bypass capac-
itor should be connected to each V
pacitor is placed as close as possible to the DS50EV401.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS50EV401.
DD
) and ground (GND) pins should be con-
DD
DD
and GND planes create
pin such that the ca-
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