MAX1402EVKIT Maxim Integrated Products, MAX1402EVKIT Datasheet - Page 16

• Manufacturer Part Number: MAX1402EVKIT
• Description: EVAL KIT FOR MAX1402
• Manufacturer: Maxim Integrated Products

Specifications of MAX1402EVKIT

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: Serial
• Inputs Per Adc: 6 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 26.7mW @ 480SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1402
• Interface Type: SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MAX1402

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
are held in reset, inhibiting normal self-timed operation.
This bit may be used to convert on command to mini-
mize the settling time to valid output data, or to synchro-
nize operation of a number of MAX1402s. FSYNC does
not reset the serial interface or the 0/DRDY flag. To clear
the 0/DRDY flag while FSYNC is active, simply read the
data register.
A1, A0: (Default = 0, 0) Channel-Selection Control Bits.
These bits (combined with the state of the DIFF, M1,
and M0 bits) determine the channel selected for con-
version according to Tables 8, 9, and 10. These bits
are ignored if the SCAN bit is set.
MF1, MF0: (Default = 0, 0) Modulator Frequency Bits.
MF1 and MF0 determine the ratio of CLKIN oscillator fre-
quency to modulator operating frequency. They affect
the output data rate, the position of the digital filter notch
frequencies, and the power dissipation of the device.
Achieve lowest power dissipation with MF1 = 0 and MF0
= 0. Highest power dissipation and fastest output data
rate occur with these bits set to 1, 1 (Table 2).
CLK: (Default = 1) CLK Bit. The CLK bit is used in con-
junction with X2CLK to tell the MAX1402 the frequency
of the CLKIN input signal. If CLK = 0, a CLKIN input fre-
quency of 1.024MHz (2.048MHz for X2CLK = 1) is
expected. If CLK = 1, a CLKIN input frequency of
2.4576MHz (4.1952MHz for X2CLK = 1) is expected.
This bit affects the decimation factor in the digital filter
and thus the output data rate (Table 2).
FS1, FS0: (Default = 0, 1) Filter Selection Bits. These
bits (in conjunction with the CLK bit) control the deci-
mation ratio of the digital filter. They determine the out-
put data rate, the position of the digital filter-frequency
response notches, and the noise present in the output
result. (Table 2).
Global Setup Register 1
Global Setup Register 2
16
Name
Defaults
Name
Defaults
FUNCTION
______________________________________________________________________________________
FUNCTION
First Bit (MSB)
First Bit (MSB)
CHANNEL SELECTION
SCAN
0
A1
0
Global Setup Register 1
MODE CONTROL
M1
0
A0
0
M0
0
MF1
0
MODULATOR
FREQUENCY
BUFF
0
MF0
FAST: (Default 0) FAST Bit. FAST = 0 causes the digi-
tal filter to perform a SINC
lator data stream. The output data rate will be deter-
mined by the values in the CLK, FS1, FS0, MF1, and
MF0 bits (Table 2). The settling time for SINC
is 3
MAX1402 automatically holds the DRDY signal false
(after any significant configuration change) until settled
data is available. FAST = 1 causes the digital filter to
perform a SINC
stream. The signal-to-noise ratio achieved with this filter
function is less than that of the SINC
SINC
than a minimum of three output sample periods for
SINC
DRDY flag will be deasserted and reasserted after the
filter has fully settled. This mode change requires a
minimum of three samples.
SCAN: (Default = 0) Scan Bit. Setting this bit to a 1
causes sequential scanning of the input channels as
determined by DIFF, M1, and M0 (see Scanning (Scan-
Mode)). When SCAN = 0, the MAX1402 repeatedly
measures the unique channel selected by A1, A0,
DIFF, M1, and M0 (Table 4).
M1, M0: (Default 0, 0) Mode Control Bits. These bits
control access to the calibration channels CALOFF and
CALGAIN. When SCAN = 0, setting M1 = 0 and M0 = 1
selects the CALOFF input, and M1 = 1 and M0 = 0
selects the CALGAIN input (Table 3). When SCAN = 1
and M1 ≠ M0, the scanning sequence includes both
CALOFF and CALGAIN inputs (Table 4). When SCAN is
set to 1 and the device is scanning the available input
channels, selection of either calibration mode (01 or 10)
will cause the scanning sequence to be extended to
include a conversion on both the CALGAIN+
/CALGAIN- input pair and the CALOFF+/CALOFF- input
0
·
1
3
. When switching from SINC
[1 / (output data rate)]. In SINC
settles in a single output sample period, rather
DIFF
0
CLK
1
1
filter function on the modulator data
BOUT
FILTER SELECTION
0
FS1
0
3
filter function on the modu-
Global Setup Register 2
1
IOUT
FS0
to SINC
0
1
3
filter; however
3
3
mode, the
mode, the
3
X2CLK
(LSB)
FAST
function
0
0
(LSB)