MAX1402EVKIT Maxim Integrated Products, MAX1402EVKIT Datasheet - Page 17

• Manufacturer Part Number: MAX1402EVKIT
• Description: EVAL KIT FOR MAX1402
• Manufacturer: Maxim Integrated Products

Specifications of MAX1402EVKIT

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: Serial
• Inputs Per Adc: 6 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 26.7mW @ 480SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1402
• Interface Type: SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MAX1402

pair. The exact sequence depends on the state of the
DIFF bit (Table 4). When scanning, the calibration
channels use the PGA gain, format, and DAC settings
defined by the contents of Transfer Function Register 3.
BUFF: (Default = 0) The BUFF bit controls operation of
the input buffer amplifiers. When this bit is 0, the inter-
nal buffers are bypassed and powered down. When
this bit is set high, the buffers drive the input sampling
capacitors and minimize the dynamic input load.
DIFF: (Default = 0) Differential/Pseudo-Differential Bit.
When DIFF = 0, the part is in pseudo-differential mode,
and AIN1–AIN5 are measured respective to AIN6, the
analog common. When DIFF = 1, the part is in differen-
tial mode with the analog inputs defined as AIN1/AIN2,
AIN3/AIN4, and AIN5/AIN6. The available input chan-
nels for each mode are tabulated in Table 5. Note that
DIFF also affects the scanning sequence when the part
is placed in SCAN mode (Table 4).
Table 2. Data Output Rate vs. CLK, Filter Select, and Modulator Frequency Bits
* Data rates offering noise-free 16-bit resolution.
Note: When FAST = 0, f
Default condition is in bold print.
Table 3. Special Modes Controlled by M1, M0 (SCAN = 0)
X2CLK = 0
2.4576
2.4576
2.4576
2.4576
CLKIN
FREQ.
f
(MHz)
1.024
1.024
1.024
1.024
CLKIN
M1
0
0
1
1
______________________________________________________________________________________
X2CLK = 1
-3dB
CLKIN
FREQ.
4.9152
4.9152
4.9152
4.9152
f
(MHz)
2.048
2.048
2.048
2.048
CLKIN
M0
0
1
0
1
+5V, 18-Bit, Low-Power, Multichannel,
= 0.262
·
Data Rate. When FAST = 1, f
Normal Mode: The device operates normally.
Calibrate Offset: In this mode the MAX1402 converts the voltage applied across CALOFF+
and CALOFF-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
Calibrate Gain: In this mode the MAX1402 converts the voltage applied across CALGAIN+
and CALGAIN-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
Reserved: Do not use.
CLK
CLK
Oversampling (Sigma-Delta) ADC
0
0
0
0
1
1
1
1
MF1
0
0
1
1
0
0
1
1
MF0
0
1
0
1
0
1
0
1
-3dB
BOUT: (Default = 0) Burn-out Current Bit. Setting BOUT
= 1 connects 100nA current sources to the selected ana-
log input channel. This mode is used to check that a
transducer has not burned out or opened circuit. The
burn-out current source must be turned off (BOUT = 0)
before measurement to ensure best linearity.
IOUT: (Default = 0) The IOUT bit controls the
Transducer Excitation Currents. A ‘0’ in this bit disables
OUT1 and OUT2 effectively making these pins high-
impedance. A ‘1’ in this location activates both IOUT1
and IOUT2 causing each pin to source 200µA.
X2CLK: (Default = 0) Times-Two Clock Bit. Setting this
bit to 1 selects a divide-by-2 prescaler in the clock sig-
nal path. This allows use of a higher frequency crystal
or clock source and improves immunity to asymmetric
clock sources.
= 0.443
FS1, FS0
(sps)*
(0, 0)
160
100
200
400
DESCRIPTION
20
40
80
50
·
Data Rate.
AVAILABLE OUTPUT DATA RATES
FS1, FS0
(sps)*
(0, 1)
100
200
120
240
480
25
50
60
FS1, FS0
(1, 0)
(sps)
1200
2400
100
200
400
800
300
600
FS1, FS0
(1, 1)
(sps)
1600
1200
2400
4800
200
400
800
600
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