MAX1402EVKIT Maxim Integrated Products, MAX1402EVKIT Datasheet - Page 8

• Manufacturer Part Number: MAX1402EVKIT
• Description: EVAL KIT FOR MAX1402
• Manufacturer: Maxim Integrated Products

Specifications of MAX1402EVKIT

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: Serial
• Inputs Per Adc: 6 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 26.7mW @ 480SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1402
• Interface Type: SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MAX1402

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
TIMING CHARACTERISTICS (continued)
(V+ = +5V ±5%, V
unless otherwise noted.) (Notes 19, 20, 21)
Figure 1. Load Circuit for Bus-Relinquish Time and V
V
8
Note 19: All input signals are specified with t
Note 20: See Figure 4.
Note 21: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
Note 22: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1402 is not in standby mode. If no
Note 23: The MAX1402 is production tested with f
Note 24: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
Note 25: For read operations, SCLK active edge is falling edge of SCLK.
Note 26: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
Note 27: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
Note 28: Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
CS Falling Edge to SCLK Falling
Edge Setup Time
Data Valid to SCLK Rising Edge
Setup Time
Data Valid to SCLK Rising Edge
Hold Time
SCLK High Pulse Width
SCLK Low Pulse Width
CS Rising Edge to SCLK Rising
Edge Hold Time
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21 & 28)
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21 & 28)
OH
_______________________________________________________________________________________
OUTPUT
Levels
PIN
TO
SCLK idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently
tied low, the part should only be operated with SCLK idling high between accesses.
clock is present, the device can draw higher current than specified.
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
careful not to allow subsequent reads to occur close to the next output update.
PARAMETER
50pF
DD
= +2.7V to +5.25V, AGND = DGND, f
at V
at V
DD
DD
= +3.3V
= +3.3V
100µA
100µA
SYMBOL
t
t
t
t
t
t
t
t
13
14
15
16
17
18
19
20
800µA
at V
200µA
at V
r
DD
DD
= t
= +5V
= +5V
f
= 5ns (10% to 90% of V
CLKIN
OL
at 2.5MHz (1MHz for some I
and
CLKIN
CONDITIONS
= 2.4576MHz; input logic 0 = 0V; logic 1 = V
DD
) and timed from a voltage level of 1.6V.
DD
tests).
MIN
100
100
30
30
40
0
0
0
TYP
DD
OL
, T
A
or V
MAX
= T
OH
MIN
limits.
UNITS
to T
ns
ns
ns
ns
ns
ns
ns
ns
MAX
,