MAX1402EVKIT Maxim Integrated Products, MAX1402EVKIT Datasheet - Page 7

• Manufacturer Part Number: MAX1402EVKIT
• Description: EVAL KIT FOR MAX1402
• Manufacturer: Maxim Integrated Products

Specifications of MAX1402EVKIT

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: Serial
• Inputs Per Adc: 6 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 26.7mW @ 480SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1402
• Interface Type: SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MAX1402

TIMING CHARACTERISTICS
(V+ = +5V ±5%, V
unless otherwise noted.) (Notes 19, 20, 21)
Note 12: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-
Note 13: V
Note 14: These specifications apply to CLKOUT only when driving a single CMOS load.
Note 15: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate cor-
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
SERIAL-INTERFACE READ OPERATION
SERIAL-INTERFACE WRITE OPERATION
Master Clock Frequency
Master Clock Input Low Time
Master Clock Input High Time
INT High Time
RESET Pulse Width Low
INT to CS Setup Time (Note 8)
SCLK Setup to Falling Edge CS
CS Falling Edge to SCLK Falling
Edge Setup Time
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
SCLK High Pulse Width
SCLK Low Pulse Width
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 21)
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
SCLK Rising Edge to INT High
(Note 27)
SCLK Setup to Falling Edge CS
tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.
rectly.
PARAMETER
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
REF
= V
DD
REFIN+
_______________________________________________________________________________________
= +2.7V to +5.25V, AGND = DGND, f
- V
+5V, 18-Bit, Low-Power, Multichannel,
REFIN-
.
SYMBOL
f
f
CLKIN LO
CLKIN HI
f
CLKIN
t
t
t
t
INT
t
t
t
t
t
t
t
t
10
11
12
2
3
4
5
6
7
8
9
Oversampling (Sigma-Delta) ADC
Crystal oscillator or clock exter-
nally supplied for specified perfor-
mance (Notes 22, 23)
t
t
X2CLK = 0, N = 2
X2CLK = 1, N = 2
V
V
V
V
V
V
CLKIN
CLKIN
DD
DD
DD
DD
DD
DD
= 5V
= 3.3V
= 5V
= 3.3V
= 5V
= 3.3V
= 1 / f
= 1 / f
CLKIN
CLKIN
CLKIN
CONDITIONS
(2
(2
= 2.4576MHz; input logic 0 = 0V; logic 1 = V
, X2CLK = 0
, X2CLK = 0
·
·
MF1 + MF0)
MF1 + MF0)
X2CLK = 0
X2CLK = 1
·
·
280 / N
560 / N
t
t
CLKIN
CLKIN
t
t
0.4
0.4
MIN
CLKIN
100
100
100
CLKIN
0.4
0.8
30
30
10
10
30
0
0
0
0
·
·
TYP
DD
, T
A
MAX
100
100
100
200
= T
2.5
5.0
80
70
MIN
to T
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
7
,