MAX1402EVKIT Maxim Integrated Products, MAX1402EVKIT Datasheet - Page 18

• Manufacturer Part Number: MAX1402EVKIT
• Description: EVAL KIT FOR MAX1402
• Manufacturer: Maxim Integrated Products

Specifications of MAX1402EVKIT

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: Serial
• Inputs Per Adc: 6 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 26.7mW @ 480SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1402
• Interface Type: SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MAX1402

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Table 4. SCAN Mode Scanning
Sequences (SCAN = 1)
Note: All other combinations reserved.
Table 5. Available Input Channels
(SCAN = 0)
Special Function Register (Write-Only)
Transfer-Function Register
18
DIFF
DIFF
Name
Defaults
Name
Defaults
0
0
0
1
1
1
0
0
0
1
1
1
______________________________________________________________________________________
FUNCTION
FUNCTION
M1
M1
0
0
1
0
0
1
0
0
1
0
0
1
M0
M0
0
1
0
0
1
0
0
1
0
0
1
0
First Bit (MSB)
First Bit (MSB)
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN
AIN1–AIN6, AIN2–AIN6,
AIN3–AIN6, AIN4–AIN6
CALOFF
CALGAIN
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6
CALOFF
CALGAIN
RESERVED BITS
G2
0
0
0
AVAILABLE CHANNELS
SEQUENCE
PGA GAIN CONTROL
G1
0
0
0
MDOUT
G0
0
0
U/B
MDOUT: (Default = 0) Modulator Out Bit. MDOUT = 0
enables data readout on the DOUT pin, the normal con-
dition for the serial interface. MDOUT = 1 changes the
function of the DOUT and INT pins, providing raw, sin-
gle-bit modulator output instead of the normal serial-
data interface output. This allows custom filtering
directly on the modulator output, without going through
the on-chip digital filter. The INT pin provides a clock to
indicate when the modulator data at DOUT should be
sampled (falling edge of INT). Note that in this mode,
the on-chip digital filter continues to operate normally.
When MDOUT is returned to 0, valid data may be
accessed through the normal serial-interface read
operation.
FULLPD: (Default = 0) Complete Power-Down Bit.
FULLPD = 1 forces the part into a complete power-down
condition, which includes the clock oscillator. The serial
interface continues to operate. The part requires a hard-
ware reset to recover correctly from this condition.
Note: Changing the reserved bits in the special-func-
tion register from the default status of all 0s will select
one of the reserved modes and the part will not operate
as expected. This register is a write-only register.
However, in the event that this register is mistakenly
read, clock 24 bits of data out of the part to restore it to
the normal interface-idle state.
The three transfer-function registers control the method
used to map the input voltage to the output codes. All
of the registers have the same format. The mapping of
control registers to associated channels depends on
the mode of operation and is affected by the state of
M1, M0, DIFF, and SCAN (Tables 8, 9, and 10).
0
0
0
RESERVED BITS
D3
0
0
0
Special Function Register (Write-Only)
OFFSET CORRECTION
D2
0
0
0
Transfer-Function Registers
D1
0
0
0
FULLPD
(LSB)
(LSB)
D0
0
0