ISL6524EVAL1 Intersil, ISL6524EVAL1 Datasheet - Page 8

• Manufacturer Part Number: ISL6524EVAL1
• Description: EVALUATION BOARD VRM8.5 ISL6524
• Manufacturer: Intersil

Specifications of ISL6524EVAL1

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 4, Non-Isolated
• Voltage - Output: 1.05 ~ 1.825V, 1.2V, 1.5V, 1.8V
• Current - Output: 14A, 1A, 1A, 1A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 200kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6524
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

The T2 to T3 time interval is dependent upon the value of
C
up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
An overvoltage on V
1, 2, and 3, and latches the IC off. An undervoltage on
V
on output 1, or an undervoltage event on output 2 or 3,
increments the respective fault counters and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re-
start. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also reset by
a successful start-up of all the outputs.
Figure 6 shows a simplified schematic of the fault logic. The
overcurrent latches are set dependent upon the states of the
overcurrent (OC1), output 2 and 3 undervoltage (UV2, UV3)
and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective C
signals). An undervoltage on either linear output (VSEN2,
3.0V
10V
SS13
OUT4
0V
0V
T0
. The same capacitor is also responsible for the ramp-
output latches the IC off. A single overcurrent event
SS24
T1
ATX 12V
SS
ATX 3.3V
ATX 5V
FIGURE 6. SOFT-START INTERVAL
pins are fully charged to above 4.0V (UP
V
T2
OUT4
OUT1
(1.8V)
T3
output (VSEN1) disables outputs
TIME
VTTPG
V
T4
8
OUT3
PGOOD
T5
(1.5V)
SS13
V
V
OUT1
OUT2
(1.65V)
(1.2V)
VSEN3, or VSEN4) is ignored until the respective UP signal
goes high. This allows V
without fault at start-up. Following an overcurrent event
(OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V
resets the overcurrent latch and generates a soft-started
ramp-up of the outputs 1, 2, and 3.
OUT1 Overvoltage Protection
The overvoltage circuit provides protection during the initial
application of power. For voltages on the VCC pin below the
power-on reset level (and above ~4V), the output level is
monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
against a shorted output. All linear regulators monitor their
respective VSEN pins for undervoltage to protect against
excessive currents.
Figure 8 illustrates the overcurrent protection with an overload
on OUT1. The overload is applied at T0 and the current
increases through the inductor (L
comparator trips when the voltage across Q1 (i
exceeds the level programmed by R
outputs 1, 2, and 3, discharges the soft-start capacitor C
with 28mA current sink, and increments the counter. Soft-start
capacitor C
up at T2 and initiates a new soft-start cycle. With OUT2 still
overloaded, the inductor current increases to trip the
overcurrent comparator. Again, this inhibits the outputs, but
the C
OC1
SS24
UV3
SS13
UV4
OV
UV2
0.8V
4V
4V
SS24
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
soft-start voltage continues increasing to above
SS13UP
SS13
DS(ON)
SS24UP
is quickly discharged. C
to monitor the current for protection
LATCH
S
R
OC
OUT3
Q
LATCH
R
S
OC
Q
POR
and V
R
COUNTER
OUT1
OCSET
OUT4
COUNTER
). At time T1, the OC1
SS13
. This inhibits
to increase
starts ramping
R
D
LATCH
INHIBIT1,2,3
FAULT
•
S
R
r
DS(ON)
Q
Q
April 18, 2005
SSDOWN
FN9015.3
FAULT
SS24
)