Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 207

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

ESPI Signals
PS025011-1010
Master-In/Slave-Out
Master-Out/Slave-In
Serial Clock
The four ESPI signals are:
•
•
•
•
The following paragraphs discuss these signals in both MASTER and SLAVE modes.
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a slave device. Data is transferred most significant bit first. The MISO pin of
a Slave device is placed in a high-impedance state if the Slave is not selected. When the
ESPI is not enabled, this signal is in a high-impedance state. The direction of this pin is
controlled by the MMEN bit of the ESPI Control Register.
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a slave device. Data is transferred most significant bit first. When the ESPI is
not enabled, this signal is in a high-impedance state. The direction of this pin is controlled
by the MMEN bit of the ESPI Control Register.
The Serial Clock (SCK) synchronizes data movement both in and out of the shift register
via the MOSI and MISO pins. In MASTER mode (MMEN = 1), the ESPI’s Baud Rate
Generator creates the serial clock and drives it out on its SCK pin to the slave devices. In
SLAVE mode, the SCK pin is an input. Slave devices ignore the SCK signal, unless their
SS pin is asserted.
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles
ESPI devices, data is shifted on one edge of the SCK and is sampled on the opposite edge
where data is stable. SCK phase and polarity is determined by the PHASE and CLKPOL
bits in the ESPI Control register.
Master-In/Slave-Out (MISO).
Master-Out/Slave-In (MOSI).
Serial Clock (SCK).
Slave Select (SS).
P R E L I M I N A R Y
(Table 113
on page 209). In both Master and Slave
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Product Specification
®
F1680 Series
193