Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 253

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 123. I
PS025011-1010
Bit Position
[7:0]
BRH
BITS
FIELD
RESET
R/W
ADDR
Note:
I
2
2
C Baud Rate High and Low Byte Registers
C Baud Rate High Byte Register (I2CBRH = 53H)
R/W
FFh
7
Value
I
The most significant byte, BRG[15:8], of the I
NAK—Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit clears the I
flushing of the I
byte is written to the I
FILTEN—I
Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This
function provides the spike suppression filter required in I
reject any input pulse with periods less than a full system clock cycle. The filters 
introduce a 3-system clock cycle latency on the inputs.
The I
combine to form a 16-bit reload value,
I
If
I 2 C Baud Rate (bits/s)
2
2
C Baud Rate High Byte
C baud rate is calculated using the following equation.
BRG
2
C Baud Rate High and Low Byte registers
=
0000H
R/W
FFh
6
2
C Signal Filter Enable
Description
2
, then use
C Data Register when an NAK condition is received after the next data
R/W
2
FFh
C Data Register. Reading this bit always returns 0.
5
=
2
10000H
C Data Register and sets the
P R E L I M I N A R Y
System Clock Frequency (Hz)
R/W
FFh
in the equation.
4
4 x BRG[15:0]
BRG
F53H
BRH
[15:0], for the I
2
R/W
FFh
C Baud Rate Generator’s reload value.
3
(Table 123
Z8 Encore! XP
TDRE
R/W
2
FFh
2
C Fast Mode. These filters
2
C Baud Rate Generator. The
and
bit to 1. This bit allows
Product Specification
Table 124
I2C Master/Slave Controller
R/W
FFh
1
®
F1680 Series
on page 239)
R/W
FFh
0
239