Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 232

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
I
2
C Interrupts
A low-pass digital filter can be applied to the SDA and SCL receive signals by setting the
Filter Enable (
glitch that is less than a system clock period in width will be rejected. This filter should be
enabled when running in I
rates.
The I
request signal to the interrupt controller. If the I
interrupt is determined by which bits are set in the I2CISTAT Register. If the I
ler is disabled, the BRG controller is used to generate general-purpose timer interrupts.
Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the data register.
Transmit Interrupts
Transmit interrupts (
both of which must be true:
•
•
Writing to the I
Receive Interrupts
Receive interrupts (
received by the I
Register. If the RDRF interrupt is not serviced prior to the completion of the next 
Receive byte, the I
until
when a Slave receives an address byte or for data bytes following a slave address that do
not match. An exception is if the Interactive Receive Mode (
I2CMODE Register, in which case Receive interrupts occur for all Receive address 
and data bytes in SLAVE mode.
Slave Address Match Interrupts
Slave address match interrupts (
I
2
C controller is in SLAVE mode and an address received matches the unique slave
The transmit data register is empty and the
The I
–
–
–
RDRF
2
C controller contains multiple interrupt sources that are combined into one interrupt
The first bit of a 10-bit address is shifted out.
The first bit of the final byte of an address is shifted out and the
deasserted.
The first bit of a data byte is shifted out.
2
C controller is enabled with one of the following:
is cleared, to prevent receive overruns. A receive interrupt does not occur 
FILTEN
2
C Data Register always clears the
2
C controller. The
2
RDRF
C controller holds SCL Low during the final data bit of the next byte
TDRE
) bit in the I
bit = 1 in I2CISTAT) occur when a byte of data has been
2
bit = 1 in I2CISTAT) occur under the following conditions, 
C FAST mode (400 Kbps), and can also be used at lower data
P R E L I M I N A R Y
SAM
2
C Control Register. When the filter is enabled, any
RDRF
bit = 1 in I2CISTAT) occur when the 
bit is cleared by reading from the I
TXI
2
C controller is enabled, the source of the
TRDE
bit = 1 in the I
Z8 Encore! XP
bit to 0.
IRM
Product Specification
I2C Master/Slave Controller
) bit is set in the
2
C Control Register.
RD
®
F1680 Series
bit is
2
C Data
2
C control-
218