Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 321

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

®
Z8 Encore! XP
F1680 Series
Product Specification
307
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of SCKSEL in the oscillator control register.
The internal precision oscillator is enabled by default. If the user code changes to a
different oscillator, it may be appropriate to disable the IPO for power savings. Disabling
the IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
The Z8 Encore! XP F1680 Series devices can generate non-maskable interrupt-like events
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate allowing execution of a clock failure vector and software
routines that either remedy the oscillator failure or issue a failure alert. This automatic
switch-over is not available, if the Watchdog Timer is the primary oscillator. It is also
unavailable if the Watchdog Timer oscillator is disabled, though it is not necessary to
enable the Watchdog Timer reset function outlined in
Watchdog Timer
chapter of this
document on page 137.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be removed from
the OSCCTL0 register).
Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a pri-
mary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by remov-
ing the WDFEN bit of the OSCCTL0 register.
The Watchdog Timer oscillator failure-detection circuit counts system clocks while
looking for a Watchdog Timer clock. The logic counts 8004 system clock cycles before
determining that a failure has occurred. The system clock rate determines the speed at
which the Watchdog Timer failure can be detected. A very slow system clock results in
very slow detection times.
PS025011-1010
P R E L I M I N A R Y
Oscillator Control