Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 257

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 128. I2CSTATE_L
Table 129. I
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
State
I2CSTATE_H
0000–0100
0110–0111
0101
1000–1111
I
Reserved
2
2
C Mode Register
C Mode Register (I2C Mode = F56H)
R
7
0
Substate
I2CSTATE_L
0000
0000
0000
0001
0111
0110
0101
0100
0011
0010
0001
0000
1000
The I
ing mode, slave address and diagnostic modes.
MODE—Selects the I
00 = MASTER/SLAVE capable (supports multi-master arbitration) with 7-bit 
2
C Mode Register (see
6
MODE[1:0]
Substate Name
—
—
Master Start
Master Restart
Send/Receive bit 7
Send/Receive bit 6
Send/Receive bit 5
Send/Receive bit 4
Send/Receive bit 3
Send/Receive bit 2
Send/Receive bit 1
Send/Receive bit 0
Send/Receive
Acknowledge
R/W
0
2
5
C controller operational mode
P R E L I M I N A R Y
Table
R/W
IRM
129) provides control over master versus slave operat-
4
0
F56H
There are no substates for these
There are no substates for these 
Sending/Receiving most significant bit
State Description
I2CSTATE_H values.
I2CSTATE_H values.
Initiating a new transaction
Master is ending one transaction and starting a
new one without letting the bus go idle.
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
GCE
R/W
3
0
Z8 Encore! XP
2
SLA[9:8]
R/W
Product Specification
I2C Master/Slave Controller
0
1
®
F1680 Series
DIAG
R/W
0
0
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