M68ICS05KJ Freescale Semiconductor, M68ICS05KJ Datasheet - Page 236

• Manufacturer Part Number: M68ICS05KJ
• Description: SIM PROGRAM FOR 68HC705KJ/J1A
• Manufacturer: Freescale Semiconductor
• Type: Simulator/Programmerr

Specifications of M68ICS05KJ

• Contents: Programmer, Power Supply, Assembler/Simulator/Debugger, Cable, Software and Documentation
• For Use With/related Products: 68HC705KJ/JIA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

GLOSSARY
CCR
clock
command set
condition codes register
CPU
CPU cycles
CPU registers
cycles
data bus
Glossary-2
Abbreviation for “condition codes register” in the MC68HC05.
The CCR has five bits (H, I, N, Z, and C) that can be used to
control conditional branch instructions. The values of the bits in
the CCR are determined by the results of previous operations. For
example, after a load accumulator (LDA) instruction, Z will be set
if the loaded value was $00.
A square wave signal that is used to sequence events in a
computer.
The command set of a CPU is the set of all operations that the CPU
knows how to perform. One way to represent an instruction set is
with a set of shorthand mnemonics such as LDA meaning “load
A.” Another representation of an instruction set is the set of
opcodes that are recognized by the CPU.
The CCR have five bits (H, I, N, Z, and C) that can be used to
control conditional branch commands. The values of the bits in the
CCR are determined by the results of previous operations. For
example, after a load accumulator (LDA) instruction, Z will be set
if the loaded value was $00.
Central Processor Unit. The part of a computer that controls
execution of instructions.
A CPU clock cycle is one period of the internal bus-rate clock.
Normally this clock is derived by dividing a crystal oscillator
source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in
CPU clock cycles.
Memory locations that are wired directly into the CPU logic
instead of being part of the addressable memory map. The CPU
always has direct access to the information in these registers. The
CPU registers in an MC68HC05 are A (8-bit accumulator), X (8-
bit index register), CCR (condition codes register containing the H,
I, N, Z, and C bits), SP (stack pointer), and PC (program counter).
See CPU cycles
A set of conductors that are used to convey binary information
from a CPU to a memory location or from a memory location to a
CPU; in the MC68HC05, the data bus is 8-bits.
M68ICS05KJOM/D