M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet
M37702E6BFS
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M37702E6BFS Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April ...
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Group 16 User’s Manual MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700 FAMILY / 7700 SERIES New publication, 1997.03 ...
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Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember ...
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Preface This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7702 Group and 7703 Group. After reading this manual, the user will be able to understand the functions, so that they can utilize their capabilities fully. For details ...
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BEFORE USING THIS MANUAL 1. Constitution This user’s manual consists of the following chapters. Refer to the chapters relevant to used products and the processor mode. Chapter 1. DESCRIPTION to Chapter 17. APPLICATION Functions which are common to all products ...
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Mask ROM Confirmation Form, PROM Confirmation Form, Mark Specification Form Copy the form in the latest data book and use it. Or, ask the contact addresses on the last page. 3. Register structure The view of the register structure is ...
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Table of Contents CHAPTER 1. DESCRIPTION 1.1 Performance overview.......................................................................................................... 1-3 1.2 Pin configuration ................................................................................................................... 1-4 1.3 Pin description ...................................................................................................................... 1-6 1.3.1 Example for processing unused pins .......................................................................... 1-9 1.4 Block diagram ...................................................................................................................... 1-12 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 ...
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Table of Contents 4.3 Interrupt control .................................................................................................................... 4-6 4.3.1 Interrupt disable flag (I) ................................................................................................ 4-8 4.3.2 Interrupt request bit ....................................................................................................... 4-8 4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ....... 4-8 4.4 Interrupt priority level ........................................................................................................ ...
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Port P6 direction register ............................................................................................. 6-7 6.3 Timer mode ............................................................................................................................ 6-8 6.3.1 Setting for timer mode ................................................................................................ 6-10 6.3.2 Count source ................................................................................................................ 6-11 6.3.3 Operation in timer mode ............................................................................................. 6-12 6.4 Event counter mode ........................................................................................................... 6-14 6.4.1 Setting for ...
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Table of Contents 8.3 A-D conversion method ..................................................................................................... 8-10 8.4 Absolute accuracy and differential non-linearity error .............................................. 8-12 8.4.1 Absolute accuracy ....................................................................................................... 8-12 8.4.2 Differential non-linearity error ..................................................................................... 8-13 8.5 One-shot mode .................................................................................................................... 8-14 8.5.1 Settings for one-shot mode ........................................................................................ ...
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CHAPTER 13. RESET 13.1 Hardware reset .................................................................................................................. 13-2 13.1.1 Pin state ..................................................................................................................... 13-3 13.1.2 State of CPU, SFR area, and internal RAM area................................................. 13-4 13.1.3 Internal processing sequence after reset ............................................................... 13-9 13.1.4 Time supplying “L” level to RESET pin ...
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Table of Contents 18.4 Electrical characteristics ................................................................................................. 18-8 18.4.1 Absolute maximum ratings ....................................................................................... 18-8 18.4.2 Recommended operating conditions ....................................................................... 18-9 18.4.3 Electrical characteristics ......................................................................................... 18-10 18.4.4 A-D converter characteristics ................................................................................. 18-11 18.4.5 Internal peripheral devices ..................................................................................... 18-12 18.4.6 Ready and ...
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Electrical characteristics ............................................................................................... 20-12 20.6 PROM version .................................................................................................................. 20-13 20.6.1 EPROM mode .......................................................................................................... 20-13 20.6.2 Bus timing and EPROM mode ............................................................................... 20-15 APPENDIX Appendix 1. Memory assignment ........................................................................................... 21-2 Appendix 2. Memory assignment in SFR area ................................................................... 21-7 Appendix ...
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Table of Contents MEMORANDUM viii 7702/7703 Group User’s Manual ...
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DESCRIPTION 1.1 Performance overview 1.2 Pin configuration 1.3 Pin description 1.4 Block diagram ...
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DESCRIPTION The 16-bit single-chip microcomputers 7702 Group and 7703 Group are suitable for office, business, and industrial equipment controllers that require high-speed processing of large amounts of data. These microcomputers develop with the M37702M2BXXXFP as the base chip. This manual ...
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Performance overview Table 1.1.1 shows the performance overview of the M37702. 7703 Group Refer to “Chapter 20. 7703 GROUP.” Table 1.1.1 M37702 performance overview Parameters Number of basic instructions Instruction execution time External clock input frequency f ...
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DESCRIPTION 1.2 Pin configuration 1.2 Pin configuration Figure 1.2.1 shows the M37702M2BXXXFP pin configuration. Figure 1.2.2 shows the M37702M2BXXXHP pin configuration. Note: For the low voltage version of the 7702 Group, refer to “Chapter 18. LOW VOLTAGE VERSION.” 7703 Group ...
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P6 /TB1 /TB0 /INT /INT /INT /TA4 /TA4 7 0 OUT ...
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DESCRIPTION 1.3 Pin description 1.3 Pin description Tables 1.3.1 to 1.3.3 list the pin description. However, the pin description in the EPROM mode of the built- in PROM version is described to section “19.2 EPROM mode.” 7703 Group The 7703 ...
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Table 1.3.2 Pin description (2) Pin Name P0 –P0 I/O port – –P1 I/O port – –P2 I/O port P2 0 ...
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DESCRIPTION 1.3 Pin description Table 1.3.3 Pin description (3) Pin Name P4 –P4 I/O port _____ HOLD, ____ RDY, P4 – _____ HOLD, ____ RDY – –P5 I/O port ...
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Example for processing unused pins Examples for processing unused pins are described below. These descriptions are just examples. The user shall modify them according to the user’s actual application and test them. (1) In single-chip mode Table 1.3.4 Example ...
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DESCRIPTION 1.3 Pin description (2) In memory expansion mode Table 1.3.5 Example for processing unused pins in memory expansion mode Pin name Ports ____ BHE (Note 2) ALE (Note 3) _____ ...
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In microprocessor mode Table 1.3.6 Example for processing unused pins in microprocessor mode Pin name Ports ____ BHE (Note 2) ALE (Note 3) _____ HLDA, (Note (Note ...
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DESCRIPTION 1.4 Block diagram 1.4 Block diagram Figure 1.4.1 shows the M37702 block diagram. Fig. 1.4.1 M37702 block diagram 1–12 7702/7703 Group User’s Manual ...
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CENTRAL PROCESSING UNIT 2.1 Central processing unit 2.2 Bus interface unit 2.3 Access space 2.4 Memory assignment 2.5 Processor modes (CPU) ...
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CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1 Central processing unit The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1. b15 b15 b15 b15 b15 b16 b15 b23 ...
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Accumulator (Acc) Accumulators A and B are available. (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It ...
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CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.4 Stack pointer (S) The stack pointer ( 16-bit register used for a subroutine call or an interrupt also used when addressing modes using the stack ...
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Program counter (PC) The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from ...
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CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.7 Data bank register (DT) The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the ...
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Bank 0 16 FFFF 16 10000 16 Bank 1 16 Notes 1 : The number of cycles required to generate an address is 1 cycle smaller when the low-order 8 bits of the DPR are “ ...
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CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.9 Processor status register (PS) The processor status register is an 11-bit register. Figure 2.1.5 shows the structure of the processor status register. b15 b14 b13 b12 b11 ...
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CENTRAL PROCESSING UNIT (CPU) (6) Bit 5: Data length flag (m) It determines whether to use a data as a 16-bit unit 8-bit unit. A data is treated as a 16- bit unit when this flag is ...
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CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2 Bus interface unit A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices. BIU’s function and operation are described below. When externally connecting devices, refer ...
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Fig. 2.2.1 Bus and bus interface unit (BIU) CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2.2 Bus interface unit 2–11 ...
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CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.2 Functions of bus interface unit (BIU) The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists the functions of each register. b23 b23 Fig. 2.2.2 ...
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The CPU and the bus send or receive data via BIU because each operates based on different clocks (Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory • I/O devices that ...
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CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.3 Operation of bus interface unit (BIU) Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). About signals which are input/output externally when accessing external devices, refer to ...
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E to Internal address bus ( Internal data bus ( Internal data bus ( ( Internal address bus ( Internal data bus ...
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CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3 Access space Figure 2.3.1 shows the M37702’s access space. By combination of the program counter (PC), which is 16 bits of structure, and the program bank register (PG), a 16-Mbyte space from ...
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Banks The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank ...
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CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 2.4 Memory assignment This section describes the internal area’s memory assignment. For more information about the external area, refer also to section “2.5 Processor modes.” 2.4.1 Memory assignment in internal area SFR (Special ...
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M37702M2BXXXFP 000000 16 SFR area 00007F 16 000080 16 Internal RAM area 00027F 16 00C000 16 Internal ROM area 00FFD6 16 00FFFF 16 : The internal memory is not allocated. Notes interrupt only for debugging; do not ...
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CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address Port P0 register Port P1 register 16 Port P0 direction register Port P1 direction register 16 Port P2 register ...
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Processor modes The M37702 can operate in 3 processor modes: single-chip mode, memory expansion mode, and microprocessor mode. Some pins’ functions, memory assignment, and access space vary according to the processor modes. This section describes the differences between the ...
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CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.1 Single-chip mode Use this mode when not using external devices. In this mode, ports function as programmable I/O ports (when using an internal peripheral device, they function as its ...
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Single-chip mode ...
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CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.1 Functions of ports each processor mode Processor modes Pins P0 P: Functions as a programmable P1 P: Functions as a programmable P2 P: Functions as a programmable ...
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Setting processor modes The voltage supplied to the CNVss pin and the processor mode bits (bits 1 and 0 at address 5E processor mode. When Vss level is supplied to CNVss pin After a reset, the microcomputer starts operating ...
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CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.2 Methods for setting processor modes Processor mode Single-chip mode Memory expansion mode Microprocessor mode Notes 1: The microcomputer starts operating in the single-chip mode after a reset. The microcomputer can be ...
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For the products operating only in the single-chip mode, be sure to set the following: •Connect the CNVss pin with Vss. •Fix the processor mode bits (bits 1 and 0 at address 5E 2. ...
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CENTRAL PROCESSING UNIT (CPU) [Precautions when selecting the processor mode] MEMORANDUM 2–28 7702/7703 Group User’s Manual ...
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INPUT/OUTPUT 3.1 Programmable I/O ports 3.2 I/O pins of internal peripheral devices PINS ...
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INPUT/OUTPUT PINS 3.1 Programmable I/O ports This chapter describes the programmable I/O ports in the single-chip mode. For P0 to P4, which change their functions according to the processor mode, refer also to the section “2.5 Processor modes” and “Chapter ...
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Direction register This register determines the input/output direction of the programmable I/O port. Each bit of this register corresponds one for one to each pin of the microcomputer. Figure 3.1.2 shows the structure of port ...
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INPUT/OUTPUT PINS 3.1 Programmable I/O ports 3.1.2 Port register Data is input/output to/from externals by writing/reading data to/from the port register. The port register consists of a port latch which holds the output data and a circuit which reads the ...
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Port Pi register ( (Addresses 2 Fig. 3.1.3 Port register structure , ...
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INPUT/OUTPUT PINS 3.1 Programmable I/O ports Figures 3.1.4 and 3.1.5 show the port peripheral circuits. [Inside dotted-line not included] Ports ...
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Ports P8 /CTS /RTS , P8 /CLK , /CTS /RTS , P8 /CLK output pin 7703 Group There are not pins P8 and Fig. ...
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INPUT/OUTPUT PINS 3.2 I/O pins of internal peripheral devices 3.2 I/O pins of internal peripheral devices P4 and also function as the I/O pins of the internal peripheral devices. Table 3.2.1 lists I/O pins 2 for the ...
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INTERRUPTS 4.1 Overview 4.2 Interrupt sources 4.3 Interrupt control 4.4 Interrupt priority level 4.5 Interrupt priority level detection circuit 4.6 Interrupt priority level detection time 4.7 Sequence from acceptance of interrupt request ...
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INTERRUPTS 4.1 Overview The suspension of the current operation in order to perform another operation owing to a certain factor is referred to as “Interrupt.” This chapter describes the interrupts. 4.1 Overview The M37702 has 19 interrupt sources to generate ...
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When an interrupt request is accepted, the contents of the registers listed below immediately preceding the acceptance of the interrupt request are automatically saved to the stack area in order of registers Program bank register (PG) Program counter (PC L ...
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INTERRUPTS 4.2 Interrupt sources 4.2 Interrupt sources Table 4.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine at the vector addresses listed in this table. Table 4.2.1 Interrupt sources ...
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Table 4.2.2 lists occurrence factors of internal interrupt request, which occur due to internal operation. Table 4.2.2 Occurrence factors of internal interrupt request Interrupt Zero division Occurs when “0” is specified as the divisor for the DIV instruction (Division instruction). ...
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INTERRUPTS 4.3 Interrupt control 4.3 Interrupt control The enabling and disabling of maskable interrupts are controlled by the following : •Interrupt request bit •Interrupt priority level select bits •Processor interrupt priority level (IPL) •Interrupt disable flag (I) The interrupt disable ...
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A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers interrupt control registers (Addresses INT ...
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INTERRUPTS 4.3 Interrupt control 4.3.1 Interrupt disable flag (I) All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts are disabled; when the flag is cleared to “0,” those interrupts are ...
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Table 4.3.1 Setting of interrupt priority level Interrupt priority level select bits Table ...
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INTERRUPTS 4.4 Interrupt priority level 4.4 Interrupt priority level When two or more interrupt requests are detected at the same sampling timing, at which whether an interrupt request exists or not is checked, in the case of the interrupt disable ...
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Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt having the highest priority level when more than one interrupt request occurs at the same sampling timing. Figure 4.5.1 shows the interrupt priority level detection ...
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INTERRUPTS 4.5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority detection circuit using Figure 4.5.2. The interrupt priority level of a requested interrupt (Y in Figure 4.5.2) is compared with the resultant priority level ...
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Interrupt priority level detection time After sampling had started, an interrupt priority level detection time has elapses before an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the interrupt ...
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INTERRUPTS 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine The sequence from the acceptance of interrupt request to the execution of the interrupt routine ...
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Sequence from acceptance of interrupt request to execution of interrupt routine Interrupt request is accepted. Interrupt request occurs. @ Instruction Instruction 2 1 Interrupt response time Time from the occurrence of an interrupt request until the completion of executing ...
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INTERRUPTS 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine 4.7.1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority ...
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Sequence from acceptance of interrupt request to execution of interrupt routine 4.7.2 Storing registers The register storing operation performed during INTACK sequence depends on whether the contents of the stack pointer (S) at accepting interrupt request are even or ...
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INTERRUPTS 4.8 Return from interrupt routine 4.9 Multiple interrupts 4.8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor ...
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Request Reset Time Interrupt 1 Interrupt priority level=3 Interrupt 2 Interrupt priority level=5 Interrupt 3 Interrupt priority level=2 Fig. 4.9.1 Multiple interrupt mechanism Nesting Main routine IPL = Interrupt ...
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INTERRUPTS 4.10 External interrupts (INT 4.10 External interrupts (INT An external interrupt request occurs by input signals to the INT interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits 5 and ...
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INT ___ Fig. 4.10.1 Structure of INT i 4.10 External interrupts (INT to INT interrupt control registers (Addresses Bit name Bit Interrupt priority level select bits ...
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INTERRUPTS 4.10 External interrupts (INT Port P6 direction register (Address 10 Fig. 4.10.2 Relationship between port P6 direction register and input pins of external interrupt 4–22 ___ interrupt Bit ...
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Function of INT interrupt request bit i (1) Selecting edge sense mode The interrupt request bit has the same function as that of internal interrupts. That is, when an interrupt request occurs, the interrupt request bit is set ...
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INTERRUPTS 4.10 External interrupts (INT Valid pin level INT i Invalid Main routine ___ Fig. 4.10.4 Occurrence of INT 4–24 ___ interrupt) i Interrupt request is accepted. First interrupt routine Second interrupt routine interrupt request in level sense mode i ...
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Switch of occurrence factor of INT To switch the occurrence factor of INT ___ INT interrupt control register in the sequence shown in Figure 4.10.5 (1). To change the polarity, set the i ___ INT interrupt control register in ...
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INTERRUPTS 4.11 Precautions when using interrupts 4.11 Precautions when using interrupts 1. Use the SEB or CLB instruction when setting the interrupt control registers (addresses change the interrupt priority level select bits (bits 0 ...
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TIMER A 5.1 Overview 5.2 Block description 5.3 Timer mode 5.4 Event counter mode 5.5 One-shot pulse mode 5.6 Pulse width modulation (PWM) mode ...
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TIMER A 5.1 Overview Timer A is used primarily for output to externals. It consists of five counters, timers A0 to A4, each equipped with a 16-bit reload function. Timers operate independently of one another. 7703 Group ...
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Block description Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described below. However, for the following registers, refer to the relevant section: •Up-down register (address 44 •One-shot start register (address ...
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TIMER A 5.2 Block description 5.2.1 Counter and reload register (timer Ai register) Each of timer Ai counter and reload register consists of 16 bits. The counter down-counts each time the count source is input. In the event counter mode, ...
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Count start register This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 5.2.2 shows the structure of the count start register ...
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TIMER A 5.2 Block description 5.2.3 Timer Ai mode register Figure 5.2.3 shows the structure of the timer Ai mode register. Operating mode select bits are used to select the operating mode of timer Ai. Bits have ...
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Timer Ai interrupt control register Figure 5.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Fig. 5.2.4 Structure of timer ...
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TIMER A 5.2 Block description 5.2.5 Port P5 and port P6 direction registers The I/O pins of Timers are shared with port P5, and the I/O pins of Timer A4 are shared with port P6. When using ...
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Timer mode In this mode, the timer counts an internally generated count source. (Refer to Table 5.3.1.) Figure 5.3.1 shows the structures of the timer Ai mode register and timer Ai register in the timer mode. Table 5.3.1 Specifications ...
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TIMER A 5.3 Timer mode (b15) (b8 Fig. 5.3.1 Structures of timer Ai mode register and timer Ai register in timer mode 5–10 Timer Ai mode ...
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Setting for timer mode Figures 5.3.2 and 5.3.3 show an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4. INTERRUPTS.” ...
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TIMER A 5.3 Timer mode Setting interrupt priority level b7 Setting port P5 and port P6 direction registers b7 b7 When gate function is selected, set the bit corresponding to the TAi Setting count start bit to “1.” b7 Fig. ...
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Count source In the timer mode, the count source select bits (bits 6 and 7 at addresses 56 source. Table 5.3.2 lists the count source frequency. Table 5.3.2 Count source frequency Count source Count source select bits b7 b6 ...
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TIMER A 5.3 Timer mode 5.3.3 Operation in timer mode When the count start bit is set to “1,” the counter starts counting of the count source. When the counter underflows, the reload register’s contents are reloaded and counting continues. ...
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Select function The following describes the selective gate and pulse output functions. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses “10 ...
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TIMER A 5.3 Timer mode n = Reload register’s contents FFFF 16 n 0000 16 “1” Count start bit “0” Count valid TAi pin’s level IN input signal Invalid level “1” Timer Ai interrupt request bit “0” The counter counts ...
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Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses “1.” When this function is selected, the TAi 16 16 pin regardless of ...
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TIMER A 5.3 Timer mode [Precautions when operating in timer mode] By reading the timer Ai register, the counter value can be read out at any timing while counting is in progress. However, if the timer Ai register is read ...
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Event counter mode In this mode, the timer counts an external signal. (Refer to Tables 5.4.1 and 5.4.2.) Figure 5.4.1 shows the structures of the timer Ai mode register and timer Ai register in the event counter mode. Table ...
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TIMER A 5.4 Event counter mode Table 5.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function with timers A2, A3, and A4) Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt ...
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Fig. 5.4.1 Structures of timer Ai mode register and timer Ai register in event counter mode Timer Ai mode register ( ...
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TIMER A 5.4 Event counter mode 5.4.1 Setting for event counter mode Figures 5.4.2 and 5.4.3 show an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. ...
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Setting interrupt priority level Setting port P5 and port P6 direction registers b7 b7 Clear the bit corresponding to the TAi When selecting the TAi bit corresponding to the TAi When selecting the two–phase pulse signal processing function, set the ...
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TIMER A 5.4 Event counter mode 5.4.2 Operation in event counter mode When the count start bit is set to “1,” the counter starts counting of the count source. The counter counts the count source’s valid edges. When the counter ...
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Switching between up-count and down-count The up-down register (address 44 count from and to the down-count. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 56 TAi pin when ...
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TIMER A 5.4 Event counter mode 5.4.3 Select functions The following describes the selective pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit ...
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Two-phase pulse signal processing function (Timers A2 to A4) For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing select bits (bits address 44 ...
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TIMER A 5.4 Event counter mode Quadruple processing The timer up-counts all rising and falling edges to the TA4 the relationship that the TA4 input signal is “H” level. The timer down-counts all rising and falling edges to the TA4 ...
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By reading the timer Ai register, the counter value can be read out at any timing while counting is in progress. However, when the timer Ai register is read at the reload ...
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TIMER A 5.5 One-shot pulse mode 5.5 One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to Table 5.5.1.) When a trigger occurs, the timer outputs “H” level from the TAi ...
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Fig. 5.5.1 Structures of timer Ai mode register and timer Ai register in one-shot pulse mode Timer Ai mode register ( ...
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TIMER A 5.5 One-shot pulse mode 5.5.1 Setting for one-shot pulse mode Figures 5.5.2 and 5.5.3 show an initial setting example for registers relevant to the one-shot pulse mode. Note that when using interrupts, set up to enable the interrupts. ...
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When external trigger is selected Setting port P5 and port P6 direction registers Set the corresponding bit to “0.” Setting count start bit to “1” Count start register (Address 40 Timer A0 count start ...
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TIMER A 5.5 One-shot pulse mode 5.5.2 Count source In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 56 the count source. Table 5.5.2 lists the count source frequency. Table 5.5.2 Count source ...
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Trigger The counter is enabled for counting when the count start bit (address 40 counting when a trigger is generated after it has been enabled. An internal or an external trigger can be selected as that trigger. An internal ...
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TIMER A 5.5 One-shot pulse mode 5.5.4 Operation in one-shot pulse mode When the one-shot pulse mode is selected with the operating mode select bits, the TAi “L” level. When the count start bit is set to “1,” the counter ...
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Reload register’s contents FFFF 16 n 0001 16 Set to “1” by software. “1” Count start bit “0” “H” TAi pin IN input signal “L” One-shot pulse “H” output from “L” TAi pin OUT Timer Ai interrupt “1” ...
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TIMER A 5.5 One-shot pulse mode [Precautions when operating in one-shot pulse mode the count start bit is cleared to “0” during counting, the counter stops counting and the reload register’s contents are reloaded into the counter, and ...
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Pulse width modulation (PWM) mode In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to Table 5.6.1.) Figure 5.6.1 shows the structures of the timer Ai mode register and timer Ai register in the ...
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TIMER A 5.6 Pulse width modulation (PWM) mode <When operating as a 16-bit pulse width modulator> (b15) (b8 <When operating as an 8-bit pulse width modulator> ...
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Setting for PWM mode Figures 5.6.2 and 5.6.3 show an initial setting example for registers relevant to the PWM mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Selecting ...
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TIMER A 5.6 Pulse width modulation (PWM) mode When external trigger is selected Setting port P5 and port P6 direction registers b7 b0 Port P5 direction register (Address D TA0 TA1 TA2 TA3 b7 b0 Port P6 direction register (Address ...
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Count source In the PWM mode, the count source select bits (bits 6 and 7 at addresses 56 source. Table 5.6.2 lists the count source frequency. Table 5.6.2 Count source frequency Count source Count source select bits b7 b6 ...
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TIMER A 5.6 Pulse width modulation (PWM) mode 5.6.4 Operation in PWM mode When the PWM mode is selected with the operating mode select bits, the TAi When a trigger is generated, the counter (pulse width modulator) starts counting and ...
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Count source “H” TAi pin’s input signal IN “L” “H” PWM pulse output from TAi pin OUT “L” “1” Timer Ai interrupt request bit “0” fi: Frequency of count source ( ...
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TIMER A 5.6 Pulse width modulation (PWM) mode Count source “H” TAi pin’s IN input signal “L” “H” 8-bit prescaler’s underflow signal “L” “H” PWM pulse output from TAi pin OUT “L” “1” Timer Ai interrupt request bit “0” fi: ...
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Fig. 5.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) 5.6 Pulse width modulation (PWM) mode 7702/7703 Group User’s Manual TIMER A 5–47 ...
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TIMER A 5.6 Pulse width modulation (PWM) mode [Precautions when operating in PWM mode the count start bit is cleared to “0” while outputting PWM pulses, the counter stops counting. When the TAi pin was outputting “H” level ...
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TIMER B 6.1 Overview 6.2 Block description 6.3 Timer mode 6.4 Event counter mode 6.5 Pulse period/pulse width mea- surement mode ...
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TIMER B 6.1 Overview 6.2 Block description Timer B consists of three counters (Timers B0 to B2) each equipped with a 16-bit reload function. Timers have identical functions and operate independently of each other. 7703 Group Timers ...
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Counter and reload register (timer Bi register) Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode The counter down-counts each time count ...
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TIMER B 6.2 Block description 6.2.2 Count start register This register is used to start and stop counting. Each bit of this register corresponds each timer. Figure 6.2.2 shows the structure of the count start register ...
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Timer Bi mode register Figure 6.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of timer Bi. Bits 2 and 3 and bits ...
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TIMER B 6.2 Block description 6.2.4 Timer Bi interrupt control register Figure 6.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” ...
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Port P6 direction register Timer Bi’s input pins are shared with port P6. When using these pins as Timer Bi’s input pins, set the corresponding bits of the port P6 direction register to “0” to set these pins for ...
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TIMER B 6.3 Timer mode 6.3 Timer mode In this mode, the timer counts an internally generated count source. (Refer to Table 6.3.1.) Figure 6.3.1 shows the structures of the timer Bi mode register and timer Bi register in the ...
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Fig. 6.3.1 Structures of timer Bi mode register and timer Bi register in timer mode Timer Bi mode register ( (Addresses ...
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TIMER B 6.3 Timer mode 6.3.1 Setting for timer mode Figure 6.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter ...
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Count source In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B source. Table 6.3.2 lists the count source frequency. Table 6.3.2 Count source frequency Count source Count source select bits b7 b6 ...
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TIMER B 6.3 Timer mode 6.3.3 Operation in timer mode When the count start bit is set to “1,” the counter starts counting of the count source. When the counter underflows, the reload register’s contents are reloaded and counting continues. ...
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By reading the timer Bi register, the counter value can be read out at any timing while counting is in progress. However, if the timer Bi register is read at the reload timing shown ...
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TIMER B 6.4 Event counter mode 6.4 Event counter mode In this mode, the timer counts an external signal. (Refer to Table 6.4.1.) Figure 6.4.1 shows the structures of the timer Bi mode register and the timer Bi register in ...
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Timer Bi mode register ( (Addresses 5B (b15) (b8 Fig. 6.4.1 Structures of timer Bi mode register and timer Bi register in event ...
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TIMER B 6.4 Event counter mode 6.4.1 Setting for event counter mode Figure 6.4.2 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, ...
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Operation in event counter mode When the count start bit is set to “1,” the counter starts counting of the count source. The counter counts the count source’s valid edges. When the counter underflows, the reload register’s contents are ...
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TIMER B 6.4 Event counter mode [Precautions when operating in event counter mode] By reading the timer Bi register, the counter value can be read out at any timing while counting is in progress. However, if the timer Bi register ...
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Pulse period/pulse width measurement mode In these mode, the timer measures an external signal’s pulse period or pulse width. (Refer to Table 6.5.1.) Figure 6.5.1 shows the structures of the timer Bi mode register and timer Bi register in ...
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TIMER B 6.5 Pulse period/pulse width measurement mode Timer Bi mode register ( (Addresses 5B Note: The timer Bi overflow flag is cleared to “0” by ...
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Setting for pulse period/pulse width measurement mode Figure 6.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to ...
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TIMER B 6.5 Pulse period/pulse width measurement mode Selecting pulse period/pulse width measurement mode and each function Setting interrupt priority level b7 b0 Setting port P6 direction register b7 Setting count start bit to “1” b7 ...
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Count source In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses select the count source Table 6.5.2 lists the count source frequency. Table 6.5.2 ...
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TIMER B 6.5 Pulse period/pulse width measurement mode 6.5.3 Operation in pulse period/pulse width measurement mode When the count start bit is set to “1,” the counter starts counting of the count source. The counter value is transferred to the ...
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Timer Bi overflow flag The timer Bi interrupt request occurs when the measurement pulse’s valid edge is input or the counter overflows. The timer Bi overflow flag is used to identify the cause of the interrupt request, that is, ...
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TIMER B 6.5 Pulse period/pulse width measurement mode Count source Measurement pulse Reload register counter Transfer timing Timing at which counter is ” cleared to “0000 16 Count start bit Timer Bi interrupt request bit Timer Bi overflow flag Counter ...
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The timer Bi interrupt request occurs by the following two causes: Input of measured pulse’s valid edge Counter overflow When the overflow is the cause of the interrupt request occurrence, ...
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TIMER B 6.5 Pulse period/pulse width measurement mode MEMORANDUM 6–28 7702/7703 Group User’s Manual ...
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SERIAL I/O 7.1 Overview 7.2 Block description 7.3 Clock synchronous serial I/O mode 7 .4 Clock asynchronous serial I/O (UART) mode ...
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SERIAL I/O 7.1 Overview This chapter describes the Serial I/O. The Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UART0 and ...
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Block description Figure 7.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below. RxD i BRG count source select bits f 2 BRGi (n+ 512 Clock ...
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SERIAL I/O 7.2 Block description 7.2.1 UARTi transmit/receive mode register Figure 7.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits is used to select UARTi’s operating mode. Bits are described in ...
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Internal/External clock select bit (bit 3) [Clock synchronous serial I/O mode] By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and ...
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SERIAL I/O 7.2 Block description 7.2.2 UARTi transmit/receive control register 0 Figure 7.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to “7.2.1 (1) Internal/External clock select bit.” ...
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UARTi transmit/receive control register 1 Figure 7.2.4 shows the structure of UARTi transmit/receive control register 1. For bits refer to each operation mode’s description UART0 transmit/receive control register ...
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SERIAL I/O 7.2 Block description (1) Transmit enable bit (bit 0) By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during transmission, UARTi enters the transmission disable state after the transmission ...
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UARTi transmit register and UARTi transmit buffer register Figure 7.2.5 shows the block diagram of transmit section; Figure 7.2.6 shows the structure of UARTi transmit buffer register Stop bit PAR : Parity bit Parity enabled 2SP SP ...
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SERIAL I/O 7.2 Block description The UARTi transmit buffer register is used to set transmit data. Set the transmit data into the low-order byte of this register when operating in the clock synchronous serial I/O mode or when a 7-bit ...
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UARTi receive register and UARTi receive buffer register Figure 7.2.7 shows the block diagram of receive section; Figure 7.2.8 shows the structure of UARTi receive buffer register Stop bit PAR : Parity bit 2SP RxD ...
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SERIAL I/O 7.2 Block description The UARTi receive register is used to convert serial data which is input to the RxD This register takes in the input signal to the RxD time. The UARTi receive buffer register is used to ...
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UARTi baud rate register (BRGi) The UARTi baud rate register (BRGi 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that a value set in the BRGi is “n” ...
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SERIAL I/O 7.2 Block description 7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be used. Each interrupt has its corresponding interrupt ...
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Interrupt priority level select bits (bits These bits select the priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupt, select priority levels When the UARTi transmit/receive ...
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SERIAL I/O 7.2 Block description 7.2.8 Port P8 direction register I/O pins of UARTi are shared with port P8. When using pins P8 set the corresponding bits of the port P8 direction register to “0” to set these pins for ...
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Clock synchronous serial I/O mode Table 7.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 7.3.2 lists the functions of I/O pins in this mode. Table 7.3.1 Performance overview in clock synchronous serial I/O ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.1 Transfer clock (synchronizing clock) Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select whether to generate the transfer clock internally or to input ...
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Method of transmission Figures 7.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions ( satisfy conditions to with the following precondition satisfied. <Precondition> The CLK pin’s input is ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 30 UART1 transmit/receive mode register (Address Clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External ...
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Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 35 ) UART1 transmit/receive control register 1 (Address Transmit buffer empty flag 0: Data present in transmit buffer ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode [When not using interrupts] Checking start of transmission UART0 transmit interrupt control register (Address 71 UART1 transmit interrupt control register (Address Interrupt request bit Checking completion of transmission. UART0 ...
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Transmit operation When the transmit conditions described in page 7-19 are satisfied, the following operations are automatically performed simultaneously. •The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register. •8 transfer clocks are generated (when an ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode UARTi transmit buffer register Transfer clock Fig. 7.3.4 Transmit operation Transfer clock “1” Transmit enable bit Data is set in UARTi transmit buffer register. “0” “1” Transmit buffer empty flag “0” “H” ...
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Method of reception Figures 7.3.6 and 7.3.7 show initial setting examples for relevant registers when receiving. Reception is started when all of the following conditions ( satisfy conditions to with the following precondition satisfied. <Precondition> The CLKi pin’s input ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 30 ) UART1 transmit/receive mode register (Address UART0 transmit/receive control register 0 (Address 34 ) UART1 transmit/receive control register 0 (Address 3C ) ...
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From preceding Figure 7.3.6 Port P8 direction register (Address UART0 receive interrupt control register (Address 72 UART1 receive interrupt control register (Address 74 b7 UART0 transmit buffer register (Address 32 UART1 transmit buffer register (Address 3A ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode [When not using interrupts] Checking completion of reception UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address Checking error UART0 transmit/receive control register 1 (Address ...
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Receive operation When the receive conditions listed on page 7-25 are satisfied, the UARTi enters the receive enable state. The receive operations are described below. The input signal of the RxD i synchronously with the rising of the clock. ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode Transmitter side Fig. 7.3.9 Connection example Transfer clock • • • UARTi receive buffer register Fig. 7.3.10 Receive operation 7–30 TxD TxD i RxD RxD i CLK CLK i MSB UARTi receive ...
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RTS i “L” 1/f CLK RxD “1” “0” “1” “0” 7702/7703 Group User’s Manual 7.3 Clock synchronous serial I/O mode EXT ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.6 Process on detecting overrun error In the clock synchronous serial I/O mode, an overrun error can be detected. (However it is impossible to detect an overrun error as the case may ...
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I/O mode] 1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. In this case, dummy ...
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SERIAL I/O 7.3 Clock synchronous serial I/O mode 6. When receiving data continuously, an overrun error cannot be detected in the following situation: when the next data reception is completed between reading the error flag by software and reading the ...