M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 493

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Interrupt priority detection time
There is a routine where a certain interrupt request should not be accepted (with enabled acceptance
of all other interrupt requests). Accordingly, the program set the interrupt priority level select bits of
the interrupt to be not accepted to “000
the interrupt request of that interrupt has been accepted immediately after the priority level had been
changed. Why did this occur and what can I do about it?
is accepted immediately after it is disabled ” if the next instruction (the LDA instruction in the above
case) is already stored in the BIU’s instruction queue buffer and conditions to accept the interrupt
request which should not be accepted are met immediately before executing the instruction which is
in that buffer.
CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into
the actual address. Detection of interrupt priority level is performed at the beginning of each instruc-
tion.
execution of the next instruction, the interrupt priority level before changing it is detected and the
interrupt request is accepted. It is because the CPU executes the next instruction before the BIU
finishes changing the interrupt priority levels.
When changing the interrupt priority level, the microcomputer can behave “as if the interrupt request
When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the
In the above case, in the interrupt priority detection which is performed simultaneously with the
A
Q
Sequence of execution
Interrupt request is
a c c e p t e d i n t h i s
interval
CPU operation
BIU operation
CLB #07H, XXXIC ; Writes “000
LDA A,DATA
(Instruction prefetch)
:
:
Previous instruction
7702/7703 Group User’s Manual
executed
2
” in order to disable it before executing the routine. However,
Interrupt request generated
; Clears interrupt request bit to “0.”
; Instruction at the beginning of the routine that
;
should not accept one certain interrupt.
CLB instruction
executed
Interrupt priority level select bits set
2
” to interrupt priority level select bits.
Interrupt request accepted
Change of interrupt priority levels
LDA instruction
executed
Appendix 6. Q & A
APPENDIX
completed
Interrupt
(1/2)
21–47