M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 295

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 13.1.5 State of SFR and internal RAM areas immediately after reset (3)
Notes 1: The access characteristics at addresses 46
Address
4C
4D
5C
5D
4A
4B
4E
5A
5B
5E
40
41
42
43
44
45
46
47
48
49
4F
50
51
52
53
54
55
56
57
58
59
5F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2: The access characteristics at addresses 50
3: The access characteristics for bit 5 at addresses 5B
4: The access characteristics for bit 1 at address 5E
Processor mode register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
mode. (Refer to “Chapter 5. TIMER A.”)
mode. (Refer to “Chapter 6. TIMER B.”)
operating mode. (Refer to “Chapter 6. TIMER B.”)
according to the voltage level supplied to the CNVss pin. (Refer to section “2.5 Processor
modes.”)
One-shot start register
Count start register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Up-down register
Register name
b7
RW
RW
RW
7702/7703 Group User’s Manual
WO
Access characteristics
RW
(Note 3)
(Note 3)
(Note 3)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
RW
RW
RW
RW
RW
RW
WO
16
16
WO
RW
RW
to 4F
to 55
RW
RW
RW
(Note4)
16
16
16
16
and its state immediately after a reset vary
RW
vary according to Timer A’s operating
vary according to Timer B’s operating
b0
to 5D
16
b7
0
0
0
0
0
State immediately after a reset
vary according to Timer B’s
?
0
0
0
0
0
0
0
?
?
?
0
0
?
?
?
0
00
00
00
00
00
00
13.1 Hardware reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
16
16
16
16
16
16
0
0
0
0
0
0
0
0
0
0
0
0
(Note 4)
0
0
0
0
0
RESET
0
0
0
0
0
0
b0
13–7