dm74als174 Fairchild Semiconductor, dm74als174 Datasheet

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dm74als174

Manufacturer Part Number
dm74als174
Description
Hex/quad D-type Flip-flops With Clear
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor Corporation
DM74ALS174M
DM74ALS174SJ
DM74ALS174N
DM74ALS175M
DM74ALS175SJ
DM74ALS175N
DM74ALS174 • DM74ALS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. Both have an asynchro-
nous clear input, and the quad (DM74ALS175) version fea-
tures complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Ordering Code
Package Number
DM74ALS174
M16A
M16D
M16A
M16D
N16E
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006112
Features
Advanced oxide-isolated ion-implanted Schottky TTL
process
Pin and functional compatible with LS family counterpart
Typical clock frequency maximum is 80 MHz
Switching performance guaranteed over full temperature
and V
Package Description
CC
supply range
DM74ALS175
September 1986
Revised February 2000
www.fairchildsemi.com

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dm74als174 Summary of contents

Page 1

... DM74ALS174 • DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchro- nous clear input, and the quad (DM74ALS175) version fea- tures complementary outputs from each flip-flop. Information at the D inputs meeting the setup time require- ments is transferred to the Q outputs on the positive-going edge of the clock pulse ...

Page 2

... HIGH Level (steady state) L LOW Level (steady state) X Don’t Care Transition from LOW-to-HIGH Level Q the level of Q before the indicated steady-state input conditions were established 0 Note 1: applies to DM74ALS175 only Logic Diagrams DM74ALS174 www.fairchildsemi.com Inputs Outputs Clock (Note ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 4

... HIGH-to-LOW Level Output From Clock www.fairchildsemi.com 5V Conditions Min 4.5V 400 4.5V to 5.5V 4. 5.5V 5.5V, V 2.7V IH 5.5V, V 0.4V IN 5.5V, V 2.25V 30 O 5.5V DM74ALS174 4.5V GND DM74ALS175 GND Conditions Min R 500 4. Typ Max Units 1 1 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M16D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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