FIN1019M Fairchild Semiconductor, FIN1019M Datasheet

IC DRVR/RCVR 3.3V HS LVDS 14SOIC

FIN1019M

Manufacturer Part Number
FIN1019M
Description
IC DRVR/RCVR 3.3V HS LVDS 14SOIC
Manufacturer
Fairchild Semiconductor
Type
Line Transceiverr
Datasheet

Specifications of FIN1019M

Number Of Drivers/receivers
1/1
Protocol
LVDS
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
FIN10
Logic Type
High Speed Differential Driver and Receiver
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Data Rate
400 Mbps
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
1 / 1
Propagation Delay Time
2.5 ns
Supply Current
12.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FIN1019M_NL
FIN1019M_NL

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© 2001 Fairchild Semiconductor Corporation
FIN1019M
FIN1019MTC
FIN1019
3.3V LVDS High Speed Differential Driver/Receiver
General Description
This driver and receiver pair are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver translates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high frequencies. This device is
ideal for high speed clock or data transfer.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
H
Z
Order Number
Open Circuit or Z
High Impedance
HIGH Logic Level
Fail Safe Condition
R
H
X
IN
L
D
H
L
X
IN
Inputs
R
Package Number
H
X
IN
L
Fail Safe
L
MTC14
M14A
LOW Logic Level
DE
H
H
H
L
RE
H
L
L
L
Open, Shorted, Terminated
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
D
OUT
H
L
Z
L
Outputs
R
X
DS500506
OUT
H
H
L
Z
Don’t Care
D
OUT
H
Z
H
L
Features
Connection Diagram
Pin Descriptions
Greater than 400Mbs data rate
3.3V power supply operation
0.5ns maximum differential pulse skew
2.5ns maximum propagation delay
Low power dissipation
Power-Off protection
100mV receiver input sensitivity
Fail safe protection open-circuit, shorted and terminated
conditions
Meets or exceeds the TIA/EIA-644 LVDS standard
Flow-through pinout simplifies PCB layout
14-Lead SOIC and TSSOP packages save space
Pin Name
D
D
Package Description
R
GND
R
R
V
D
OUT
OUT
DE
RE
NC
OUT
IN
IN
CC
IN
LVTTL Data Input
Non-inverting LVDS Output
Inverting LVDS Output
Driver Enable (LVTTL, Active HIGH)
Non-Inverting LVDS Input
Inverting LVDS Input
LVTTL Receiver Output
Receiver Enable (LVTTL, Active LOW)
Power Supply
Ground
No Connect
April 2001
Revised September 2001
Description
www.fairchildsemi.com

Related parts for FIN1019M

FIN1019M Summary of contents

Page 1

... FIN1019M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow FIN1019MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Absolute Maximum Ratings Supply Voltage ( LVTTL DC Input Voltage (D , DE, RE) IN LVDS DC Input Voltage ( LVTTL DC Output Voltage (R ) OUT LVDS DC Output Voltage (D , ...

Page 3

DC Electrical Characteristics Device Characteristics I Power Supply Current CC C Input Capacitance IN C Output Capacitance OUT Note 2: All typical values are and with Electrical Characteristics Over supply voltage and ...

Page 4

FIGURE 1. Differential Driver DC Test Circuit FIGURE 3. AC Waveforms for Differential Driver FIGURE 5. Enable and Disable AC Waveforms www.fairchildsemi.com Note A: Input pulses have frequency 10 MHz Note B: C includes all probe ...

Page 5

Note A: Input pulses have frequency 10 MHz Note B: C includes all probe and fixture capacitance L FIGURE 6. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 1. Receiver ...

Page 6

FIGURE 7. LVDS Input to LVTTL Output AC Waveforms Voltage Waveforms Enable and Disable Times FIGURE 8. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com Test Circuit for LVTTL Outputs 6 ...

Page 7

Typical Performance Curves Drivers FIGURE 9. Output High Voltage vs. Power Supply Voltage FIGURE 11. Output Short Circuit Current vs. Power Supply Voltage FIGURE 13. Differential Output Voltage vs. Load Resistor FIGURE 10. Output Low Voltage vs. ...

Page 8

Typical Performance Curves FIGURE 15. Power Supply Current vs. Frequency FIGURE 17. Power Supply Current vs. Ambient Temperature FIGURE 19. Differential Propagation Delay vs. Ambient Temperature www.fairchildsemi.com (Continued) FIGURE 16. Power Supply Current vs. Power Supply Voltage ...

Page 9

Typical Performance Curves FIGURE 21. Differential Pulse Skew (t PLH Ambient Temperature (Continued vs. PHL FIGURE 22. Transition Time vs. Power Supply Voltage FIGURE 23. Transition Times vs. Ambient Temperature 9 www.fairchildsemi.com ...

Page 10

Typical Performance Curves Receiver FIGURE 24. Output High Voltage vs. Power Supply Voltage FIGURE 26. Output Short Circuit Current vs. Power Supply Voltage FIGURE 28. Power Supply Current vs. Power Supply Voltage www.fairchildsemi.com FIGURE 25. Output Low ...

Page 11

Typical Performance Curves FIGURE 30. Differential Propagation Delay vs. Power Supply Voltage FIGURE 32. Differential Skew ( PHL Power Supply Voltage FIGURE 34. Differential Propagation Delay vs. Differential Input Voltage (Continued) FIGURE 31. Differential Propagation ...

Page 12

Typical Performance Curves FIGURE 36. Transition Time vs. Power Supply Voltage FIGURE 38. Differential Propagation Delay vs. Load www.fairchildsemi.com (Continued) FIGURE 37. Transition Time vs. Ambient Temperature FIGURE 39. Transition Time vs. Load 12 ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 13 www.fairchildsemi.com ...

Page 14

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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