mm74hc175 Fairchild Semiconductor, mm74hc175 Datasheet
mm74hc175
Manufacturer Part Number
mm74hc175
Description
Quad D-type Flip-flop With Clear
Manufacturer
Fairchild Semiconductor
Datasheet
1.MM74HC175.pdf
(7 pages)
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© 1999 Fairchild Semiconductor Corporation
MM74HC175M
MM74HC175SJ
MM74HC175MTC
MM74HC175N
MM74HC175
Quad D-Type Flip-Flop With Clear
General Description
The MM74HC175 high speed D-type flip-flop with comple-
mentary outputs utilizes advanced silicon-gate CMOS
technology to achieve the high noise immunity and low
power consumption of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
Information at the D inputs of the MM74HC175 is trans-
ferred to the Q and Q outputs on the positive going edge of
the clock pulse. Both true and complement outputs from
each flip flop are externally available. All four flip-flops are
controlled by a common clock and a common CLEAR.
Clearing is accomplished by a negative pulse at the
CLEAR input. All four Q outputs are cleared to a logical “0”
and all four Q outputs to a logical “1.”
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignments for DIP, SOIC, SOP and TSSOP
Package Number
Top View
MTC16
M16D
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005319.prf
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
Features
Truth Table
H
L
X
Q
established
0
Typical propagation delay: 15 ns
Wide operating supply voltage range: 2–6V
Low input current: 1 A maximum
Low quiescent supply current: 80 A maximum (74HC)
High output drive current: 4 mA minimum (74HC)
LOW Level (steady state)
Transition from LOW-to-HIGH level
Irrelevant
HIGH Level (steady state)
The level of Q before the indicated steady-state input conditions were
Package Description
Clear
L
H
H
H
Inputs
(Each Flip-Flop)
CC
Clock
and ground.
X
L
September 1983
Revised February 1999
D
X
H
X
L
Q
Outputs
Q
H
L
L
0
www.fairchildsemi.com
Q
Q
H
H
L
0
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Datasheet:
mm74hc175 Summary of contents
Page 1
... CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Information at the D inputs of the MM74HC175 is trans- ferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available ...
Page 2
Logic Diagram www.fairchildsemi.com 2 ...
Page 3
Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) OUT DC ...
Page 4
AC Electrical Characteristics Symbol Parameter f Maximum Operating MAX Frequency Maximum Propagation PHL PLH Delay, Clock ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16A Package Number M16D 5 www.fairchildsemi.com ...
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC16 6 ...
Page 7
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...