PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet - Page 407

• Manufacturer Part Number: PIC18F2420-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2420-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS39631E-page 405
CLKO and I/O............................................................344
Clock Synchronization...............................................181
Clock/Instruction Cycle................................................57
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0).......................349
Example SPI Master Mode (CKE = 1).......................350
Example SPI Slave Mode (CKE = 0).........................351
Example SPI Slave Mode (CKE = 1).........................353
External Clock (All Modes Except PLL) ....................342
Fail-Safe Clock Monitor (FSCM) ...............................262
First Start Bit Timing..................................................189
Full-Bridge PWM Output ...........................................153
Half-Bridge PWM Output...........................................152
High/Low-Voltage Detect Characteristics..................339
High-Voltage Detect Operation (VDIRMAG = 1) .......246
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation (VDIRMAG = 0)........245
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4420/4520) ....................348
Parallel Slave Port (PSP) Read ................................121
Parallel Slave Port (PSP) Write.................................121
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change.............................................155
PWM Direction Change at Near
PWM Output..............................................................144
Repeated Start Condition..........................................190
Reset, Watchdog Timer, Oscillator Start-up
Send Break Character Sequence .............................216
Slave Synchronization...............................................167
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ..........................................166
SPI Mode (Slave Mode, CKE = 0).............................168
SPI Mode (Slave Mode, CKE = 1).............................168
Synchronous Reception (Master Mode, SREN)........219
Synchronous Transmission .......................................217
Synchronous Transmission (Through TXEN) ...........218
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data .............................................................354
C Bus Start/Stop Bits..............................................354
C Master Mode (7 or 10-Bit Transmission).............192
C Master Mode (7-Bit Reception) ...........................193
C Slave Mode (10-Bit Reception, SEN = 0)............178
C Slave Mode (10-Bit Reception, SEN = 1)............183
C Slave Mode (10-Bit Transmission) ......................179
C Slave Mode (7-Bit Reception, SEN = 0)..............176
C Slave Mode (7-Bit Reception, SEN = 1)..............182
C Slave Mode (7-Bit Transmission) ........................177
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode .........194
(Master/Slave)...................................................359
(Master/Slave)...................................................358
Sequence (7 or 10-Bit Addressing Mode) .........184
Auto-Restart Disabled)......................................158
Auto-Restart Enabled).......................................158
100% Duty Cycle...............................................155
Timer, Power-up Timer .....................................345
V
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
DD
Rise > T
2
2
C Bus Data .........................................356
C Bus Start/Stop Bits..........................356
PWRT
DD
) .............................................47
) ............................................47
DD
DD
, Case 1) ........................46
, Case 2) ........................46
DD
,
PIC18F2420/2520/4420/4520
Timing Diagrams and Specifications................................. 342
Top-of-Stack Access........................................................... 54
TRISE Register
TSTFSZ ............................................................................ 307
Two-Speed Start-up.................................................. 249, 260
Two-Word Instructions
TXSTA Register
V
Voltage Reference Specifications ..................................... 338
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock ........................... 346
Transition for Entry to Idle Mode................................. 38
Transition for Entry to SEC_RUN Mode ..................... 35
Transition for Entry to Sleep Mode ............................. 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to
Transition for Wake from Sleep (HSPLL) ................... 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ...................................... 36
A/D Conversion Requirements ................................. 360
Capture/Compare/PWM (CCP)
CLKO and I/O Requirements .................................... 344
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements ................................... 342
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................. 343
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
PSPMODE Bit........................................................... 114
Example Cases........................................................... 58
BRGH Bit .................................................................. 205
2
C Bus Data Requirements (Slave Mode) ............... 355
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 260
Run Mode ........................................................... 38
PRI_RUN Mode .................................................. 36
PRI_RUN Mode (HSPLL) ................................... 35
Requirements ................................................... 347
Requirements ................................................... 359
Requirements ................................................... 358
(Master Mode, CKE = 0) ................................... 349
(Master Mode, CKE = 1) ................................... 350
(Slave Mode, CKE = 0) ..................................... 352
(Slave Mode, CKE = 1) ..................................... 353
Requirements ................................................... 357
Requirements ................................................... 356
(PIC18F4420/4520) .......................................... 348
Timer, Power-up Timer and Brown-out
Reset Requirements ......................................... 345
Requirements ................................................... 346
2
2
C Bus Data
C Bus Start/Stop Bits
© 2008 Microchip Technology Inc.
DD
, V
DD
Rise < T
PWRT
) ............ 46