PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet - Page 67

• Manufacturer Part Number: PIC18F2420-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2420-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-2:
© 2008 Microchip Technology Inc.
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
PWM1CON
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
MSSP Receive Buffer/Transmit Register
A/D Result Register High Byte
A/D Result Register Low Byte
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Bytes
Timer2 Register
Timer2 Period Register
MSSP Address Register in I
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
VDIRMAG
ECCPASE
TMR0ON
ABDOVF
P1M1
PRSEN
CVREN
C2OUT
IDLEN
WCOL
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY (CONTINUED)
(2)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ECCPAS2
ACKSTAT
T3CCP2
P1M0
PDC6
CVROE
T1RUN
SSPOV
C1OUT
T08BIT
RCIDL
IRCF2
Bit 6
CKE
—
—
—
—
—
—
(2)
(2)
(1)
2
C™ Slave Mode. MSSP Baud Rate Reload Register in I
ECCPAS1
T1CKPS1
T3CKPS1
PDC5
SSPEN
ACKDT
VCFG1
ACQT2
RXDTP
DC1B1
DC2B1
IRVST
C2INV
IRCF1
CVRR
T0CS
CHS3
Bit 5
D/A
—
—
(2)
PIC18F2420/2520/4420/4520
ECCPAS0
T1CKPS0
T3CKPS0
HLVDEN
PDC4
ACKEN
CVRSS
VCFG0
ACQT1
DC1B0
DC2B0
TXCKP
IRCF0
C1INV
CHS2
T0SE
Bit 4
CKP
—
RI
P
(2)
T1OSCEN
CCP1M3
CCP2M3
PSSAC1
T3CCP1
HLVDL3
PDC3
SSPM3
PCFG3
ACQT0
BRG16
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
TO
—
S
(2)
TMR2ON
T1SYNC
CCP1M2
CCP2M2
PSSAC0
T3SYNC
HLVDL2
PDC2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
PEN
CM2
R/W
PD
—
—
(2)
2
PSSBD1
GO/DONE
T2CKPS1
TMR1CS
C Master Mode.
CCP1M1
CCP2M1
TMR3CS
HLVDL1
PDC1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
WUE
Bit 1
POR
CM1
UA
—
(2)
(2)
PSSBD0
SWDTEN
T2CKPS0
TMR1ON
TMR3ON
CCP1M0
CCP2M0
HLVDL0
PDC0
ABDEN
SSPM0
PCFG0
ADCS0
T0PS0
ADON
SCS0
CVR0
Bit 0
BOR
SEN
CM0
BF
(2)
(2)
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0100 0-00
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
--- ---0
DS39631E-page 65
Value on
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50, 169,
50, 162,
50, 163,
51, 139,
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50, 125
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50, 245
50, 259
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50, 133
50, 170
50, 173
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51, 140
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51, 204
51, 156
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51, 239
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42, 48,
30, 50
102
170
171
172
147