PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet - Page 81
![IC PIC MCU FLASH 8KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2420-I/ML
Manufacturer Part Number
PIC18F2420-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2420-IML.pdf
(412 pages)
2.PIC18F2420-IML.pdf
(16 pages)
3.PIC18F2420-IML.pdf
(8 pages)
4.PIC18F2420-IML.pdf
(6 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(4 pages)
7.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F2420-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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6.5
The minimum programming block is 16 words or
32 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 32 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed
32 times for each programming operation. All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 32 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
FIGURE 6-5:
6.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
© 2008 Microchip Technology Inc.
TBLPTR = xxxxx0
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the row erase procedure.
Load Table Pointer register with address of first
byte being written.
Write the 32 bytes into the holding registers with
auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
8
TABLE WRITES TO FLASH PROGRAM MEMORY
TBLPTR = xxxxx1
Holding Register
PIC18F2420/2520/4420/4520
8
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Holding Register
Note:
Note:
Disable interrupts.
Write 55h to EECON2.
2 ms using internal timer).
8
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means indi-
vidual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 32 holding registers
before executing a write operation.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 32 bytes in
the holding register.
TBLPTR = xxxx3F
Holding Register
DS39631E-page 79
8
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