PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet - Page 68

• Manufacturer Part Number: PIC18F2420-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2420-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2420/2520/4420/4520
TABLE 5-2:
DS39631E-page 66
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
TRISA7
PSPIP
PSPIF
PSPIE
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
EEPGD
RA7
CSRC
SPEN
Bit 7
RD7
RC7
RB7
IBF
—
—
(5)
PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY (CONTINUED)
(2)
(5)
(2)
(2)
(5)
TRISA6
PLLEN
LATA6
RA6
CFGS
CMIP
CMIF
CMIE
ADIP
ADIE
Bit 6
ADIF
OBF
RD6
RC6
TX9
RX9
RB6
—
—
(5)
(5)
(3)
(5)
PORTA Data Direction Register
PORTA Data Latch Register (Read and Write to Data Latch)
TXEN
SREN
RCIP
RCIF
RCIE
IBOV
Bit 5
RD5
RC5
RB5
RA5
—
—
—
—
—
—
—
PSPMODE
SYNC
CREN
FREE
TUN4
EEIP
EEIF
EEIE
TXIP
TXIE
Bit 4
TXIF
RD4
RC4
RB4
RA4
—
—
WRERR
ADDEN
SENDB
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
RE3
TUN3
Bit 3
RD3
RC3
RB3
RA3
—
—
(4)
PORTE Data Latch Register
(Read and Write to Data Latch)
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TRISE2
WREN
BRGH
RE2
FERR
TUN2
Bit 2
RD2
RC2
RB2
RA2
(2)
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISE1
OERR
RE1
TRMT
TUN1
Bit 1
RD1
RC1
RB1
RA1
WR
(2)
© 2008 Microchip Technology Inc.
TMR1IP
TMR1IE
CCP2IP
CCP2IF
CCP2IE
TMR1IF
TRISE0
RE0
RX9D
TUN0
TX9D
Bit 0
RD0
RC0
RB0
RA0
RD
(2)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000 51, 74, 83
0000 0000 51, 74, 83
0000 0000 51, 74, 83
xx-0 x000 51, 75, 84
11-1 1111
00-0 0000
00-0 0000
1111 1111
0000 0000
0000 0000
0q-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
POR, BOR
Value on
on page:
Details
51, 206
51, 206
51, 213
51, 211
51, 202
51, 203
52, 101
52, 100
52, 118
52, 114
52, 108
52, 105
52, 117
52, 114
52, 108
52, 105
52, 117
52, 114
52, 108
52, 105
52, 111
52, 111
52, 111
52, 97
52, 99
52, 96
52, 98
27, 52