DSPIC33FJ16GS504-I/PT Microchip Technology, DSPIC33FJ16GS504-I/PT Datasheet - Page 158

• Manufacturer Part Number: DSPIC33FJ16GS504-I/PT
• Description: IC DSPIC MCU/DSP 16K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS504-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
10.1.1
In addition to the PORT, LAT and TRIS registers for
data control, some digital-only port pins can also be
individually configured for either digital or open-drain
output. This is controlled by the Open-Drain Control
register, ODCx, associated with each port. Setting any
of the bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than V
desired digital only pins by using external pull-up
resistors. The maximum open-drain voltage allowed is
the same as the maximum V
Refer to “Pin Diagrams” for the available pins and
their functionality.
10.2
The ADPCFG and TRIS registers control the operation
of the Analog-to-Digital (A/D) port pins. The port pins
that are to function as analog inputs must have their
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (V
will be converted.
The ADPCFG register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EQUATION 10-1:
DS70318D-page 156
MOV
MOV
NOP
BTSS
0xFF00, W0
W0, TRISBB
PORTB, #13
Configuring Analog Port Pins
OPEN-DRAIN CONFIGURATION
PORT WRITE/READ EXAMPLE
DD
(for example, 5V) on any
IH
specification.
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
OH
or V
Preliminary
OL
)
10.2.1
One instruction cycle is required between a port direction
change or port write operation and a read operation of
the same port. Typically, this instruction would be a NOP.
An example is shown in Example 10-1.
10.3
The input change notification function of the I/O
ports
dsPIC33FJ16GSX02/X04 devices to generate interrupt
requests to the processor
Change-Of-State (COS) on selected input pins. This
feature can detect input Change-Of-States even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, up to 30 external signals (CNx
pin) can be selected (enabled) for generating an
interrupt request on a Change-Of-State.
Four control registers are associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
the push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Note:
allows
Input Change Notification
I/O PORT WRITE/READ TIMING
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
the
dsPIC33FJ06GS101/X02
© 2009 Microchip Technology Inc.
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