AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 101
![IC MCU AVR32 256KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0256-ALUT
Manufacturer Part Number
AT32UC3A0256-ALUT
Description
IC MCU AVR32 256KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0256-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0256-ALUT
Manufacturer:
ATMEL
Quantity:
167
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16.4
16.4.1
16.4.2
32058J–AVR32–04/11
User Interface
Memory Map
Interrupt Request Map
pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
This chapter lists the INTC registers are accessible through the PB bus. The registers are used
to control the behaviour and read the status of the INTC.
The following table shows the address map of the INTC registers, relative to the base address of
the INTC.
Table 16-1.
The mapping of interrupt requests from peripherals to INTREQs is presented in the Peripherals
Section.
Offset
0
4
...
252
256
260
...
508
512
516
520
524
Register
Interrupt Priority Register 0
Interrupt Priority Register 1
...
Interrupt Priority Register 63
Interrupt Request Register 0
Interrupt Request Register 1
...
Interrupt Request Register 63
Interrupt Cause Register 3
Interrupt Cause Register 2
Interrupt Cause Register 1
Interrupt Cause Register 0
INTC address map
Name
IPR0
IPR1
...
IPR63
IRR0
IRR1
...
IRR63
ICR3
ICR2
ICR1
ICR0
Access
Read/Write
Read/Write
...
Read/Write
Read-only
Read-only
...
Read-only
Read-only
Read-only
Read-only
Read-only
Reset Value
0x0000_0000
0x0000_0000
...
0x0000_0000
N/A
N/A
...
N/A
N/A
N/A
N/A
N/A
AT32UC3A
101
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