AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 516

• Manufacturer Part Number: AT32UC3A0256-ALUT
• Description: IC MCU AVR32 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0256-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.7.2.12
30.7.2.12.1 Overview
Figure 30-17. Example of an IN Endpoint with 1 Data Bank
32058J–AVR32–04/11
TXINI
FIFOCON
Management of IN Endpoints
SW
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request has priority over any other request and has to be ACKed. This means that
any other flag should be cleared and the FIFO reset when a SETUP is received.
The firmware has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written by the firmware which acknowledges or not the bank when it is full.
The endpoint must be configured first.
The TXINI bit is set by hardware at the same time as FIFOCON when the current bank is free.
This triggers an EPXINT interrupt if TXINE = 1.
TXINI shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt, what
has no effect on the endpoint FIFO.
The firmware then writes into the FIFO and clears the FIFOCON bit to allow the USB controller
to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next
bank. The TXINI and FIFOCON bits are updated by hardware in accordance with the status of
the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not full, i.e. the software can write
further data into the FIFO.
write data to CPU
NAK
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear flag and return
if TXINI, then continue
BANK 0
SW
IN
(bank 0)
DATA
HW
ACK
SW
write data to CPU
BANK 0
AT32UC3A
SW
IN
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