AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 619
![IC MCU AVR32 256KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0256-ALUT
Manufacturer Part Number
AT32UC3A0256-ALUT
Description
IC MCU AVR32 256KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0256-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0256-ALUT
Manufacturer:
ATMEL
Quantity:
167
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• CURRBK: Current Bank
For non-control pipe, set by hardware to indicate the number of the current bank.
Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt flag.
• RWALL: Read/Write Allowed
For OUT pipe, set by hardware when the current bank is not full, i.e. the software can write further data into the FIFO.
For IN pipe, set by hardware when the current bank is not empty, i.e. the software can read further data from the FIFO.
Cleared by hardware otherwise.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set.
• CFGOK: Configuration OK Status
This bit is updated when the ALLOC bit is set.
Set by hardware if the pipe X number of banks (PBK) and size (PSIZE) are correct compared to the maximal allowed num-
ber of banks and size for this pipe and to the maximal FIFO size (i.e. the DPRAM size).
If this bit is cleared by hardware, the user should reprogram the UPCFGX register with correct PBK and PSIZE values.
• PBYCT: Pipe Byte Count
Set by the hardware to indicate the byte count of the FIFO.
For OUT pipe, incremented after each byte written by the software into the pipe and decremented after each byte sent to
the peripheral.
For In pipe, incremented after each byte received from the peripheral and decremented after each byte read by the soft-
ware from the pipe.
Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt flag.
32058J–AVR32–04/11
0
0
1
1
CURRBK
0
1
0
1
Current Bank
Bank0
Bank1
Bank2
Reserved
AT32UC3A
619
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