P89LV51RD2BBC,557 NXP Semiconductors, P89LV51RD2BBC,557 Datasheet - Page 41

• Manufacturer Part Number: P89LV51RD2BBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89LVr

Specifications of P89LV51RD2BBC,557

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P89LV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: 89LV
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1289; 935274177557; P89LV51RD2BBC

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
Fig 15. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor
communications is enabled
The following examples help to show the versatility of this scheme.
Example 1, slave 0:
Example 2, slave 1:
In the above example value SADDR is the same and the SADEN data is used to
differentiate between the two slaves. Slave 0 requires a ‘0’ in bit 0 and it ignores bit 1.
Slave 1 requires a ‘0’ in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be
1100 0010 since slave 1 requires a ‘0’ in bit 1. A unique address for slave 1 would be 1100
0001 since a ‘1’ in bit 0 will exclude slave 0. Both slaves can be selected at the same time
by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could
be addressed with 1100 0000.
SADDR = 1100 0000
--------------------------------------------------- -
SADDR = 1100 0000
--------------------------------------------------- -
SADEN = 1111 1101
SADEN = 1111 1110
rx_byte(7)
rx_byte(0)
Given = 1100 00X0
Given = 1100 000X
saden(7)
saden(0)
saddr(7)
saddr(0)
saddr(7)
saddr(0)
logic used by UART to detect 'given address' in received data
logic used by UART to detect 'given address' in received data
rx_byte(7)
rx_byte(0)
saden(7)
saden(0)
Rev. 05 — 15 December 2009
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given_address_match
broadcast_address_match
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
002aaa527
© NXP B.V. 2009. All rights reserved.
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