P89LV51RD2BBC,557 NXP Semiconductors, P89LV51RD2BBC,557 Datasheet - Page 61

• Manufacturer Part Number: P89LV51RD2BBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89LVr

Specifications of P89LV51RD2BBC,557

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P89LV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: 89LV
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1289; 935274177557; P89LV51RD2BBC

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
Table 58.
Table 59.
Not Bit addressable; reset value: xxxx x0xxB.
Table 60.
Device
P89LV51RB2/RC2/RD2 12
Bit
7
6
5 to 4
3
2 to 0
Bit
Symbol
Clock doubling features
FST - Flash status register (address B6) bit allocation
FST - Flash status register (address B6) bit descriptions
Symbol
-
SB
-
EDC
-
7
-
Rev. 05 — 15 December 2009
SB
Standard mode (X1)
Clocks per
machine cycle
6
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Security bit.
Reserved for future use. Should be set to ‘0’ by user programs.
Enable double clock.
Reserved for future use. Should be set to ‘0’ by user programs.
5
-
Maximum
external clock
frequency (MHz)
33
P89LV51RB2/RC2/RD2
4
-
8-bit microcontrollers with 80C51 core
EDC
3
Clock double mode (X2)
Clocks per
machine cycle
6
2
-
© NXP B.V. 2009. All rights reserved.
Maximum
external clock
frequency (MHz)
16
1
-
61 of 76
0
-