ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 119

• Manufacturer Part Number: ST72F324LJ2T5
• Description: IC MCU 8BIT 8K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324LJ2T5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8242; ST72F324LJ2T5

CLOCK CHARACTERISTICS (Cont’d)
12.5.5 PLL Characteristics
Note:
1. Instantaneous PLL jitter is the absolute maximum deviation on a single clock period. Data characterized, not tested in
production.
Figure 64. PLL Clock Jitter vs. Application
Signal frequency
Note 1: Measurement conditions: f
V
f
OSC
∆ f
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Operating Range
PLL input frequency range
Instantaneous PLL jitter
Application Signal Frequency (KHz)
1
1000
Parameter
500
250
CPU
1)
FLASH
DEVICES
ROM
DEVICES
= 4MHz, T
125
f
OSC
= 4 MHz. (f
A
Conditions
= 25°C
PLL clock jitter may cause application errors if high
frequency signals are input or output by the appli-
cation (e.g. high speed serial I/O or sampling of
high frequency signals).
Using the PLL increases clock jitter, however this
is a periodic effect which is absorbed over several
CPU cycles. The lower the frequency of the appli-
cation signal, the less the impact.
Figure 64
out PLL) on application signals in the range
125kHz to 2MHz. At frequencies of less than
125kHz, the jitter is negligible.
CPU
=8MHz.)
shows the effect of jitter (with and with-
2.85
Min
2
Typ
3.5
ST72324Lxx
Max
3.6
5.5
4
119/154
MHz
Unit
%
V
1