ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 98

• Manufacturer Part Number: ST72F324LJ2T5
• Description: IC MCU 8BIT 8K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324LJ2T5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8242; ST72F324LJ2T5

ST72324Lxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
Read/Write
Reset Value: 0000 0000 (00 h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
Table 22. Baudrate Selection
98/154
1
ERPR
Symbol
7
7
f
f
Rx
Tx
ERPR
6
Communication frequency 8 MHz
ERPR
5
Parameter
ERPR
4
Figure
ERPR
3
ERPR
52) is divided by
2
f
CPU
ERPR
1
Accuracy vs
Standard
~0.16%
~0.79%
ERPR
0
0
Conditions
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Reset Value:0000 0000 (00 h)
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
ETPR
7
7
ETPR
Prescaler
6
ETPR
5
ETPR
4
Standard
Figure
ETPR
3
10400
19200
38400
14400 ~14285.71
1200
2400
4800
9600
300
ETPR
52) is divided by
2
~10416.67
~19230.77
~38461.54
~1201.92
~2403.84
~4807.69
~9615.38
Baud
~300.48
Rate
ETPR
1
ETPR
Unit
Hz
0
0