ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 31
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ST72F324LJ2T5
Manufacturer Part Number
ST72F324LJ2T5
Description
IC MCU 8BIT 8K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F324LJ2T5.pdf
(154 pages)
Specifications of ST72F324LJ2T5
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-10°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 10 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8242
ST72F324LJ2T5
ST72F324LJ2T5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324LJ2T5
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324LJ2T5
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST72F324LJ2T5TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
INTERRUPTS (Cont’d)
Table 9. Interrupt Mapping
Notes:
1. Valid for ROM devices. For Flash devices only a RESET or MCC/RTC interrupt can be used to wake-
up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■
■
■
N°
10
Falling edge
Rising edge
Falling and rising edge
0
1
2
3
4
5
6
7
8
9
18). This control allows to have up to 4 fully
MCC/RTC
TIMER A
TIMER B
Source
RESET
Block
TRAP
SCI
SPI
ei0
ei1
ei2
ei3
Reset
Software interrupt
Main clock controller time base inter-
rupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Not used
Not used
Description
■
■
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared when disabling
these interrupts by setting their I0_x and I1_x in
the matching ISPR
Register
MCCSR
SPICSR
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
SCISR
TASR
TBSR
Label
N/A
N/A
Priority
Priority
Priority
Higher
Order
Lower
HALT
from
Exit
yes
yes
yes
yes
yes
yes
no
no
no
no
no
Active
HALT
from
yes
yes
yes
yes
yes
Exit
yes
yes
no
no
no
no
1)
1)
1)
1)
1)
ST72324Lxx
FFECh-FFEDh
FFFCh-FFFDh
FFEEh-FFEFh
FFEAh-FFEBh
FFFEh-FFFFh
FFFAh-FFFBh
FFE8h-FFE9h
FFE6h-FFE7h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Address
Vector
31/154
1