MC9S08JM60CGT Freescale Semiconductor, MC9S08JM60CGT Datasheet - Page 152

• Manufacturer Part Number: MC9S08JM60CGT
• Description: IC MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM60CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 37
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Package: 48QFN EP
• Family Name: HCS08
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: DEMOJM - KIT DEMO FOR JM MCU FAMILYDEMOJMSKT - BOARD DEMO S08JM CARD W/SOCKET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC12V1)
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered.
However, they continue to be the values transferred after the completion of the last successful conversion.
If the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
10.4.4.4
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum
value for f
10.4.4.5
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (
After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5
ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is
isolated from the input channel and a successive approximation algorithm is performed to determine the
digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon
completion of the conversion algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
sample is enabled (ADLSMP=1).
152
The maximum total conversion time for different conditions is summarized in
Single or first continuous 10-bit or 12-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 10-bit or 12-bit
Subsequent continuous 10-bit or 12-bit;
Subsequent continuous 10-bit or 12-bit;
ADCK
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Subsequent continuous 8-bit;
Subsequent continuous 8-bit;
ADCK
frequency, precise sample time for continuous conversions cannot be guaranteed when long
Power Control
Sample Time and Total Conversion Time
Conversion Type
f
f
BUS
BUS
f
f
BUS
BUS
(see the electrical specifications).
> f
> f
> f
> f
ADCK
ADCK
ADCK
ADCK
Table 10-13. Total Conversion Time vs. Control Conditions
/11
/11
MC9S08JM60 Series Data Sheet, Rev. 3
ADCK
frequency, precise sample time for continuous conversions
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
ADLSMP
0
0
1
1
0
0
1
1
0
0
1
1
23 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
20 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
Max Total Conversion Time
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
Table
Freescale Semiconductor
10-13.
f
ADCK
).