MC9S08JM60CGT Freescale Semiconductor, MC9S08JM60CGT Datasheet - Page 52
![IC MCU 8BIT 60K FLASH 48-QFN](/photos/12/17/121757/mc9s08jm60cgt_sml.jpg)
MC9S08JM60CGT
Manufacturer Part Number
MC9S08JM60CGT
Description
IC MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08JM32CLD.pdf
(388 pages)
Specifications of MC9S08JM60CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
37
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Total Internal Ram Size
4KB
# I/os (max)
37
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Package
48QFN EP
Family Name
HCS08
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
For Use With
DEMOJM - KIT DEMO FOR JM MCU FAMILYDEMOJMSKT - BOARD DEMO S08JM CARD W/SOCKET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4 Memory
4.5.2
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (f
(see
normally this write is done during reset initialization. FCDIV cannot be written if the access error flag,
FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV
register. One period of the resulting clock (1/f
and erase pulses. An integer number of these timing pulses are used by the command processor to complete
a program or erase command.
Table 4-5
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
4.5.3
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
52
1. Write a data value to an address in the flash array. The address and data information from this write
Section 4.7.1, “Flash Clock Divider Register
is latched into the flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For page erase commands,
the address may be any address in the 512-byte page of flash to be erased. For mass erase and blank
check commands, the address can be any address in the flash memory. Whole pages of 512 bytes
are the smallest block of flash that may be erased. In the 60K version, there are two instances where
the size of a block that is accessible to the user is less than 512 bytes: the first page following RAM,
and the first page following the high page registers. These pages are overlapped by the RAM and
high page registers respectively.
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
FCLK
Program and Erase Times
Program and Erase Command Execution
1
Byte program
Byte program (burst)
Page erase
Mass erase
Do not program any byte in the flash more than once after a successful erase
operation. Reprogramming bits to a byte which is already programmed is
not allowed without first erasing the page in which the byte resides or mass
erasing the entire flash memory. Programming without first erasing may
disturb data stored in the flash.
Excluding start/end overhead
). The time for one cycle of FCLK is t
Parameter
Table 4-5. Program and Erase Times
MC9S08JM60 Series Data Sheet, Rev. 3
Cycles of FCLK
FCLK
NOTE
20,000
(FCDIV).”) This register can be written only once, so
4000
) is used by the command processor to time program
9
4
FCLK
= 1/f
FCLK
FCLK
FCLK
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
) between 150 kHz and 200 kHz
100 ms
20 μs
20 ms
45 μs
1
Freescale Semiconductor
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