MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 224

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 7 Analog-to-Digital Converter (ATD10B8CV3)
7.3.2.11
Read: Anytime
Write: Anytime
7.3.2.12
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified
in the device overview. The port pins are shared with the analog A/D inputs AN7–0.
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general purpose digital input.
224
Function
PTAD[7:0]
IEN[7:0]
Reset
Reset
Field
Field
7–0
7–0
Pin
W
W
R
R
PTAD7
IEN7
AN7
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled
(IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read
returns the logic level on ANx pin (signal potentials not meeting V
indeterminate value).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD0 bits to “1”.
ATD Input Enable Register (ATDDIEN)
Port Data Register (PORTAD)
0
1
7
7
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
= Unimplemented or Reserved
PTAD6
IEN6
AN6
0
1
6
6
Figure 7-13. ATD Input Enable Register (ATDDIEN)
Figure 7-14. Port Data Register (PORTAD)
Table 7-21. ATDDIEN Field Descriptions
Table 7-22. PORTAD Field Descriptions
PTAD5
IEN5
AN5
MC9S12NE64 Data Sheet, Rev. 1.1
0
1
5
5
PTAD4
IEN4
AN4
0
1
4
4
Description
Description
PTAD3
IEN3
AN3
0
1
3
3
IL
or V
PTAD2
IH
IEN2
AN2
0
1
2
2
specifications will have an
Freescale Semiconductor
PTAD1
IEN1
AN1
0
1
1
1
PTAD0
IEN0
AN0
0
1
0
0