MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 433

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
2
16.3.2.8
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
Freescale Semiconductor
ROM_SW[1:0]
PAG_SW[1:0]
The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009.
Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
Reset
ram_sw2:ram_sw0
Field
7:6
1:0
W
R ROM_SW1
101
110
111
Memory Size Register 1 (MEMSIZ1)
—
Allocated System FLASH or ROM Physical Memory Space — The allocated system FLASH or ROM
physical memory space is as given in
Allocated Off-Chip FLASH or ROM Memory Space — The allocated off-chip FLASH or ROM memory space
size is as given in
7
As stated, the bits in this register provide read visibility to the system
physical memory space allocations defined at system integration. The actual
array size for any given type of memory block may differ from the allocated
size. Please refer to the device overview chapter for actual sizes.
= Unimplemented or Reserved
ROM_SW0
—
Table 16-9. Allocated RAM Memory Space (continued)
6
RAM Space
Figure 16-10. Memory Size Register 1 (MEMSIZ1)
Allocated
12K bytes
14K bytes
16K bytes
Table
Table 16-10. MEMSIZ0 Field Descriptions
16-12.
MC9S12NE64 Data Sheet, Rev. 1.1
—
0
5
Mappable Region
Table
16K bytes
16K bytes
16K bytes
NOTE
—
0
4
16-11.
RAM
Description
2
2
—
0
3
RAM[15:14]
RAM[15:14]
RAM[15:14]
Bits Used
INITRM
—
0
2
Memory Map and Register Definition
PAG_SW1
—
1
Base Address
RAM Reset
0x1000
0x0800
0x0000
PAG_SW0
—
0
1
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