MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 493

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.4.2.3
The definitions of begin- and end-trigger as used in the DBG module are as follows:
18.4.2.4
In DBG mode, arming occurs by setting DBGEN and ARM in DBGC1. The ARM bit in DBGC1 is cleared
when the trigger condition is met in end-trigger mode or when the Trace Buffer is filled in begin-trigger
mode. The TBC logic determines whether a trigger condition has been met based on the trigger mode and
the trigger selection.
18.4.2.5
The DBG module supports nine trigger modes. The trigger modes are encoded as shown in
The trigger mode is used as a qualifier for either starting or ending the storing of data in the trace buffer.
When the match condition is met, the appropriate flag A or B is set in DBGSC. Arming the DBG module
clears the A, B, and C flags in DBGSC. In all trigger modes except for the event-only modes and DETAIL
capture mode, change-of-flow addresses are stored in the trace buffer. In the event-only modes only the
value on the data bus at the trigger event B will be stored. In DETAIL capture mode address and data for
all cycles except program fetch (P) and free (f) cycles are stored in trace buffer.
18.4.2.5.1
In the A only trigger mode, if the match condition for A is met, the A flag in DBGSC is set and a trigger
occurs.
18.4.2.5.2
In the A or B trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is
set and a trigger occurs.
18.4.2.5.3
In the A then B trigger mode, the match condition for A must be met before the match condition for B is
compared. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The
trigger occurs only after A then B have matched.
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Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are
filled.
End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of
the trace buffer if more than 64 words are collected.
Begin- and End-Trigger
Arming the DBG Module
Trigger Modes
A Only
A or B
A then B
When tagging and using A then B, if addresses A and B are close together,
then B may not complete the trigger sequence. This occurs when A and B
are in the instruction queue at the same time. Basically the A trigger has not
yet occurred, so the B instruction is not tagged. Generally, if address B is at
MC9S12NE64 Data Sheet, Rev. 1.1
NOTE
Functional Description
Table
18-6.
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