MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 55

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Signal Description
1.2.3.46 PL0 / ACTLED — Port L I/O Pin 0
PL0 is a general-purpose I/O pin. When the internal Ethernet physical transceiver (EPHY) is enabled with
the EPHYCTL0 LEDEN bit set, it becomes the active status signal (ACTLED). While in reset and
immediately out of reset, the PL0 pin is configured as a high-impedance input pin. See the port integration
module (PIM) PIM_9NE64 block description chapter and the EPHY block description chapter for
information about pin configurations.
1.2.3.47 PS7 / SPI_SS — Port S I/O Pin 7
PS7 is a general-purpose I/O. When the serial peripheral interface (SPI) is enabled, PS7 becomes the slave
select pin SS. While in reset and immediately out of reset, the PS7 pin is configured as a high-impedance
input pin. See the port integration module (PIM) PIM_9NE64 block description chapter and the SPI block
description chapter for information about pin configurations.
1.2.3.48 PS6 / SPI_SCK — Port S I/O Pin 6
PS6 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS6 becomes the
serial clock pin, SCK. While in reset and immediately out of reset, the PS6 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the SPI block description chapter for information about pin configurations.
1.2.3.49 PS5 / SPI_MOSI — Port S I/O Pin 5
PS5 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS5 becomes the
master output (during master mode) or slave input (during slave mode) pin. While in reset and immediately
out of reset, the PS5 pin is configured as a high-impedance input pin. See the port integration module
(PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about
pin configurations.
1.2.3.50 PS4 / SPI_MISO — Port S I/O Pin 4
PS4 is a general-purpose I/O pin. When the serial peripheral interface (SPI) is enabled, PS4 becomes the
master input (during master mode) or slave output (during slave mode) pin. While in reset and immediately
out of reset, the PS4 pin is configured as a high-impedance input pin. See the port integration module
(PIM) PIM_9NE64 block description chapter and the SPI block description chapter for information about
pin configurations.
1.2.3.51 PS3 / SCI1_TXD — Port S I/O Pin 3
PS3 is a general-purpose I/O. When the serial communications interface 1 (SCI1) transmitter is enabled,
PS3 becomes the transmit pin, TXD, of SCI1. While in reset and immediately out of reset, the PS3 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
55