MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 434

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 16 Module Mapping Control (MMCV4)
16.3.2.9
Read: Anytime
Write: Determined at chip integration. Generally it’s: “write anytime in all modes;” on some devices it will
be: “write only in special modes.” Check specific device documentation to determine which applies.
Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with
write only in special modes), see device overview chapter.
434
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
Reset
actual reset state of this register.
W
R
1
Program Page Index Register (PPAGE)
—
0
7
As stated, the bits in this register provide read visibility to the system
memory space and on-chip/off-chip partitioning allocations defined at
system integration. The actual array size for any given type of memory
block may differ from the allocated size. Please refer to the device overview
chapter for actual sizes.
NOTES:
1. The ROMHM software bit in the MISC register determines the accessibility of the
FLASH/ROM memory space. Please refer to
1
(MEMSIZ1),” for a detailed functional description of the ROMHM bit.
pag_sw1:pag_sw0
= Unimplemented or Reserved
Table 16-11. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0
—
0
6
00
01
10
11
Figure 16-11. Program Page Index Register (PPAGE)
Table 16-12. Allocated Off-Chip Memory Options
00
01
10
11
PIX5
MC9S12NE64 Data Sheet, Rev. 1.1
—
5
Off-Chip Space
876K bytes
768K bytes
512K bytes
PIX4
NOTE
0K byte
—
4
Section 16.3.2.8, “Memory Size Register
PIX3
—
3
Allocated FLASH
or ROM Space
48K bytes
64K bytes
16K bytes
0K byte
On-Chip Space
128K bytes
256K bytes
512K bytes
PIX2
—
1M byte
2
(1)
(1)
Freescale Semiconductor
PIX1
—
1
PIX0
—
0