M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet
M30853FJGP#U3
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M30853FJGP#U3 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M32C/80 Series 16/ 32 Software Manual RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to ...
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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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This manual is written for the M32C/80 Series software. This manual can be used for all types of MCUs having the M32C/80 Series CPU core. The reader of this manual is expected to have the basic knowledge of electric and ...
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M16C Family Documents The following documents were prepared for the M16C Family.* Document Shortsheet Hardware overview Datasheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description ...
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Chapter 1 Overview .............................................................................................. 1.1 Features of M32C/80 Series .................................................................................. 2 1.2 Address Space ....................................................................................................... 3 1.3 Register Configuration ........................................................................................... 4 1.4 Flag Register (FLG) ............................................................................................... 7 1.5 Register Bank ......................................................................................................... 9 1.6 Internal State after Reset ..................................................................................... 10 1.7 ...
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Chapter 5 Interrupt ............................................................................................... 5.1 Outline of Interrupt ............................................................................................. 308 5.2 Interrupt Control ................................................................................................. 312 5.3 Interrupt Sequence ............................................................................................. 314 5.4 Return from Interrupt Routine ............................................................................ 317 5.5 Interrupt Priority .................................................................................................. 318 5.6 Multiple Interrupts ............................................................................................... 318 5.7 Precautions for ...
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Quick Reference in Alphabetic Order Mnemonic See page for function ABS 43 ADC 44 ADCF 45 ADD 46 ADDX 48 ADJNZ 49 AND 50 BAND 52 BCLR 53 BITINDEX 54 Cnd BM 55 BMEQ/Z 55 BMGE 55 BMGEU/C 55 BMGT ...
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Quick Reference in Alphabetic Order Mnemonic See page for function JMP JMPI JMPS JSR JSRI JSRS LDC LDCTX 100 LDIPL 101 MAX 102 MIN 103 MOV 104 MOVA 106 Dir MOV 107 MOVHH 107 MOVHL 107 MOVLH 107 MOVLL 107 ...
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Quick Reference by Function Mnemonic Function Transfer MOV MOVA MOVDir MOVX POP POPC POPM PUSH PUSHA PUSHM STNZ STZ STZX XCHG Bit BAND manupulation BCLR BITINDEX Cnd BM BNAND BNOR BNOT BNTST BNXOR BOR BSET BTST BTSTC BTSTS BXOR Shift ...
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Quick Reference by Function Mnemonic Function Arithmetic CLIP CMP CPMX DADC DADD DEC DIV DIVU DIVX DSBB DSUB EXTS EXTZ INC MAX MIN MUL MULEX MULU NEG RMPA SBB SUB SUBX Logical AND NOT OR TST XOR Jump ADJNZ SBJNZ ...
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Quick Reference by Function Mnemonic Function String SMOVB SMOVF SMOVU SOUT SSTR Other BRK BRK2 ENTER EXITD FCLR FREIT FSET INDEX Type INT INTO LDC LDCTX LDIPL NOP POPC PUSHC REIT STC STCTX cnd SC UND WAIT Content Transfer string ...
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Quick Reference by Addressing (general instruction addressing) Mnemonic *2 *3 ABS ADC *2 *3 ADCF * ADD ADDX * ADJNZ * AND BITINDEX *2 *3 CLIP *2 *3 CMP CMPX ...
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Quick Reference by Addressing (general instruction addressing) Mnemonic INT *1 JMP JMPI * JMPS * JSRI JSRS * LDC LDIPL MAX * MIN *1 MOV MOVA ...
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Quick Reference by Addressing (general instruction addressing) Mnemonic PUSHM *1 ROLC * RORC ROT *2 *3 SBB * SBJNZ SCCnd * SHA *12 *13 SHANC SHL SHLNC *12 *13 *1 ...
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Quick Reference by Addressing (special instruction addressing) Mnemonic *1 ADD *1 ADJNZ Cnd J *1 JMP *1 JSR *1 LDC POPC *1 POPM PUSHC *1 PUSHM *1 SBJNZ *1 STC * 1 Has general instruction addressing. Addressing Quick reference-9 See ...
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Quick Reference by Addressing (bit instruction addressing) Mnemonic BAND BCLR Cnd BM BNAND BNOR BNOT BNTST BNXOR BOR BSET BTST BTSTC BTSTS BXOR FCLR FSET Addressing Quick reference-10 See page See page for function for instruction code /number of cycles ...
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Features of M32C/80 Series 1.2 Address Space 1.3 Register Configuration 1.4 Flag Register (FLG) 1.5 Register Bank 1.6 Internal State after Reset 1.7 Data Types 1.8 Data Arrangement 1.9 Instruction Format 1.10 Vector Table Chapter 1 Overview ...
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Chapter 1 Overview 1.1 Features of M32C/80 Series The M32C/80 Series is a single-chip MCU developed for built-in applications where the MCU is built into applications equipment. The M32C/80 Series supports instructions suitable for the C language with frequently used ...
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Chapter 1 Overview 1.2 Address Space Fig. 1.2.1 shows an address space. Addresses 000000 through 0003FF 16 models of the M32C/80 Series, the SFR area extends from 0003FF Addresses from 000400 on make up a memory area. In individual models ...
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Chapter 1 Overview 1.3 Register Configuration Figure 1.3.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, FB, and SB) out of 28 CPU registers. There are two sets of register ...
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Chapter 1 Overview (1) Data Registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0, and R3R1) These registers consist of 16 bits, and are used primarily for transfers and arithmetic/logic operations. Registers R0 and R1 can be halved into ...
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Chapter 1 Overview (11) Vector Register (VCT) This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is generated. (12) DMA Mode Registers (DMD0/DMD1) These registers consist of 8 bits and are ...
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Chapter 1 Overview 1.4 Flag Register (FLG) Figure 1.4.1 shows a configuration of the flag register (FLG). The function of each flag is detailed below. (1) Bit 0: Carry Flag (C flag) This flag holds a carry, borrow, or shifted-out ...
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Chapter 1 Overview (10) Bits 12-14: Processor Interrupt Priority Level (IPL) The processor interrupt priority level (IPL) consists of three bits, allowing you to specify eight processor interrupt priority levels from level 0 to level requested interrupt's ...
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Chapter 1 Overview 1.5 Register Bank The M32C/80 has two register banks, each configured with data registers (R0, R1, R2, and R3), address registers (A0 and A1), frame base register (FB), and static base register (SB). These two register banks ...
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Chapter 1 Overview 1.6 Internal State after Reset The following lists the content of each register after a reset. • Data registers (R0, R1, R2, and R3) • Address registers (A0 and A1) • Static base register (SB) • Frame ...
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Chapter 1 Overview 1.7 Data Types There are four data types: integer, decimal, bit, and string. 1.7.1 Integer An integer can be a signed or an unsigned integer. A negative value of a signed integer is represented by two's complement. ...
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Chapter 1 Overview 1.7.3 Bits (1) Register bits Figure 1.7.3 shows register bit specification. Register bits can be specified by register direct (bit,RnH/RnL or bit,An). Use bit,RnH/RnL to specify a bit in data register (RnH/RnL); use bit,An to specify a ...
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Chapter 1 Overview (1) Bit specification by bit, base Figure 1.7.5 shows the relationship between memory map and bit map. Memory bits can be handled as an array of consecutive bits. Bits can be specified by a given combina- tion ...
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Chapter 1 Overview (2) SB/FB relative bit specification For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set to static base register (SB) or frame base register (FB) plus the address set ...
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Chapter 1 Overview 1.7.4 String String is a type of data that consists of a given length of consecutive byte (8-bit) or word (16-bit) data. This data type can be used in seven types of string instructions: character string backward ...
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Chapter 1 Overview 1.8 Data Arrangement 1.8.1 Data Arrangement in Register Figure 1.8.1 shows the relationship between a register's data size and bit numbers. Nibble (4-bit) data Byte (8-bit) data Word (16-bit) data Long word (32-bit) data Figure 1.8.1 Data ...
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Chapter 1 Overview 1.8.2 Data Arrangement in Memory Figure 1.8.2 shows data arrangement in memory. Figure 1.8.3 shows some examples of operation. N N+1 N+2 N+3 N N+1 N+2 N+3 24-bit (Address) data Figure 1.8.2 Data arrangement in memory MOV.B ...
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Chapter 1 Overview 1.9 Instruction Format The instruction format can be classified into four types: generic, quick, short, and zero. The number of bytes in the instruction that can be chosen by a given format is least for the zero ...
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Chapter 1 Overview 1.10 Vector Table The vector table comes in two types: a special page vector table and an interrupt vector table. The special page vector table is a fixed vector table. The interrupt vector table can be a ...
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Chapter 1 Overview 1.10.2 Variable Vector Table The variable vector table is an address-variable vector table. Specifically, this vector table is a 256-byte interrupt vector table that uses the value indicated by the interrupt table register (INTB) as the entry ...
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Addressing Modes 2.1 Addressing Modes 2.2 Guide to This Chapter 2.3 General Instruction Addressing 2.4 Indirect Instruction Addressing 2.5 Special Instruction Addressing 2.6 Bit Instruction Addressing 2.7 Read and write operations with 24-bit registers Chapter 2 ...
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Chapter 2 Addressing Modes 2.1 Addressing Modes This section describes addressing mode-representing symbols and operations for each addressing mode. The M32C/80 has four addressing modes outlined below. (1) General instruction addressing This addressing accesses an area from address 000000 The ...
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Chapter 2 Addressing Modes 2.2 Guide to This Chapter The following shows how to read this chapter using an actual example. (1) Address register relative The value indicated by displacement dsp:8[A0] (2) (dsp) plus the content of address dsp:8[A1] register ...
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Chapter 2 Addressing Modes 2.3 General Instruction Addressing Immediate The immediate data indicated by #IMM #IMM is the object to be operated on. #IMM8 #IMM16 #IMM32 Register direct The specified register is the object to R0L be operated on. R0H ...
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Chapter 2 Addressing Modes Address register relative The value indicated by displacement dsp:8[A0] (dsp) plus the content of address dsp:8[A1] register (A0/A1) added not including dsp:16[A0] the sign bits constitutes the effective address to be operated on. dsp:16[A1] dsp:24[A0] However, ...
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Chapter 2 Addressing Modes Stack pointer relative dsp:8[SP] The address indicated by the content of stack pointer (SP) plus the value indicated by displacement (dsp) added including the sign bits consti- tutes the effective address to be operated on. The ...
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Chapter 2 Addressing Modes 2.4 Indirect Instruction Addressing Absolute indirect [abs16] The 4-byte value indicated by absolute addressing constitutes the effective [abs24] address to be operated on. The effective address range is 0000000 to 0FFFFFF 16 Two-stage address register indirect ...
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Chapter 2 Addressing Modes Address register relative indirect The 4-byte value indicated by [dsp:8[A0]] address register relative constitutes [dsp:8[A1]] the effective address to be operated [dsp:16[A0]] on. [dsp:16[A1]] The effective address range is [dsp:24[A0]] 0000000 to 0FFFFFF 16 [dsp:24[A1]] SB ...
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Chapter 2 Addressing Modes FB relative indirect The 4-byte value indicated by FB [dsp:8[FB]] relative constitutes the effective [dsp:16[FB]] address to be operated on. The effective address range is 0000000 to 0FFFFFF 16 Indirecting addressing mode cannot be used since ...
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Chapter 2 Addressing Modes 2.5 Special Instruction Addressing Control register direct The specified control register is the INTB object to be operated on. ISP SP This addressing can be used in LDC and STC instructions you specify ...
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Chapter 2 Addressing Modes Program counter relative • When the jump length specifier label (.length) is (.S)... the base address plus the value indicated by displacement (dsp) added not including the sign bits constitutes the effective ad- dress. This addressing ...
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Chapter 2 Addressing Modes 2.6 Bit Instruction Addressing This addressing can be used in the following instructions: BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BM BTSTC Register direct The specified register bit is the object bit,R0L ...
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Chapter 2 Addressing Modes Address register relative bit,base:11[A0] The bit that is as much away from bit 0 at the address indi- bit,base:11[A1] cated by base as the number of bit,base:19[A0] bits indicated by address regis- ter (A0/A1) is the ...
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Chapter 2 Addressing Modes FB relative The bit that is as much away bit,base:11[FB] from bit 0 at the address indi- bit,base:19[FB] cated by frame base register (FB) plus the value indicated by base (added including the sign bit) as ...
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Chapter 2 Addressing Modes 2.7 Read and write operations with 24-bit registers This section describes operation when 24 bits register (A0, A1) is src or dest for each size specifier (.size .L). When (.B) is specified for the ...
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Chapter 2 Addressing Modes When (.W) is specified for the size specifier (.size) • Read The low order 16-bit are read. The flags change states depending on the result of 16-bit operation. • Write Write to the low order 16-bit. ...
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Chapter 3 Functions 3.1 Guide to This Chapter 3.2 Functions 3.3 Index Instructions ...
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Chapter 3 Functions 3.1 Guide to This Chapter This chapter describes the functionality of each instruction by showing syntax, operation, function, select- able src/dest, flag changes, and description examples. The following shows how to read this chapter by using an ...
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Chapter 3 Functions (1) Mnemonic Indicates the mnemonic explained in this page. (2) Instruction code/number of cycles Indicates the page in which instruction code/number of cycles is listed. Refer to this page for instruction code and number of cycles. (3) ...
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Chapter 3 Functions Chapter 3 Functions OR (1) (2) [ Syntax ] (3) OR.size (:format) src,dest [ Operation ] (4) dest src dest [src] [ Function ] (5) • This instruction logically ORs • When (.W) is specified for the ...
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Chapter 3 Functions (4) Operation Explains the operation of the instruction using symbols. (5) Function Explains the function of the instruction and precautions to be taken when using the instruction. (6) Selectable src / dest (label) If the instruction has ...
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Chapter 3 Functions The following explains the syntax of each jump instruction JMP, JPMI, JSR, and JSRI by using an actual example. Chapter 3 Functions JMP (1) (2) [ Syntax ] (3) JMP (.length) label (3) Syntax Indicates the instruction ...
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Chapter 3 Functions 3.2 Functions ABS [ Syntax ] ABS.size dest [ Operation ] dest dest [dest] [dest] [ Function ] • This instruction takes on an absolute value of • When (.W) is specified for the size specifier (.size) ...
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Chapter 3 Functions ADC [ Syntax ] ADC.size src,dest [ Operation ] dest src + dest [ Function ] dest • This instruction adds • When (.B) is specified for the size specifier (.size) and extended to be treated as ...
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Chapter 3 Functions ADCF [ Syntax ] ADCF.size dest [ Operation ] dest dest + C [dest] [dest Function ] dest • This instruction adds • When (.W) is specified for the size specifier (.size) and high-order ...
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Chapter 3 Functions ADD [ Syntax ] ADD.size (:format) [ Operation ] dest dest + src dest dest + [src] [ Function ] dest • This instruction adds and • When (.B) is specified for the size specifier (.size) and ...
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Chapter 3 Functions [src/dest Classified by Format format* src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3 A0/A0/A0* A1/A1/A1* [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB] dsp:24[A0] dsp:24[A1] abs24 #IMM8/#IMM16/#IMM32 *4 Indirect instruction addressing [src] and [dest] can be ...
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Chapter 3 Functions ADDX [ Syntax ] ADDX src,dest [ Operation ] dest dest + EXTS(src) dest dest + EXTS([src]) [ Function ] src • Sign-extend the 8-bit dest • When is the address register (A0, A1) , operation. The ...
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Chapter 3 Functions ADJNZ [ Syntax ] ADJNZ.size src,dest,label [ Operation ] dest dest + src if dest 0 then jump label [ Function ] dest • This instruction adds • When the addition resulted in any value other than ...
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Chapter 3 Functions AND [ Syntax ] AND.size (:format) [ Operation ] dest src dest dest [src] dest [ Function ] • This instruction logically ANDs • When (.B) is specified for the size specifier (.size) and extended to be ...
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Chapter 3 Functions [src/dest Classified by Format format* src R0L/R0/R2R0 R0H/R2/- R1L/R1/R2R0 R1H/R3 A0/A0/A0* A1/A1/A1* [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB] dsp:24[A0] dsp:24[A1] abs24 #IMM8/#IMM16 *3 Indirect instruction addressing [src] and [dest] can be ...
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Chapter 3 Functions BAND [ Syntax ] BAND src [ Operation ] C src C [ Function ] • This instruction logically ANDs the C flag and src • When is the address register (A0, A1), you can specify the ...
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Chapter 3 Functions BCLR [ Syntax ] BCLR dest [ Operation ] dest 0 [ Function ] • This instruction stores 0 in dest • When is the address register (A0, A1), you can specify the 8 low-order bits for ...
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Chapter 3 Functions BITINDEX [ Syntax ] BITINDEX.size src [ Operation ] [ Function ] • This instruction modifies addressing of the next bit instruction. • No interrupt request is accepted immediately after this instruction. • The operand specified in ...
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Chapter 3 Functions BM Cnd [ Syntax ] BM Cnd dest [ Operation ] if true then dest 1 else dest 0 [ Function ] • This instruction transfers the true or false value of the condition indicated by condition ...
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Chapter 3 Functions BNAND [ Syntax ] BNAND src [ Operation ] ______ C src C [ Function ] • This instruction logically ANDs the C flag and inverted src • When is the address register (A0, A1), you can ...
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Chapter 3 Functions BNOR [ Syntax ] BNOR src [ Operation ] ______ C src C [ Function ] • This instruction logically ORs the C flag and inverted src • When is the address register (A0, A1), you can ...
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Chapter 3 Functions BNOT [ Syntax ] BNOT dest [ Operation ] ________ dest dest [ Function ] dest • This instruction inverts dest • When is the address register (A0, A1), you can specify the 8 low-order bits for ...
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Chapter 3 Functions BNTST [ Syntax ] BNTST src [ Operation ] Z src ______ C src [ Function ] • This instruction transfers inverted src • When is the address register (A0, A1), you can specify the 8 low-order ...
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Chapter 3 Functions BNXOR [ Syntax ] BNXOR src [ Operation ] ______ A C src C [ Function ] • This instruction exclusive ORs the C flag and inverted src • When is the address register (A0, A1), you ...
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Chapter 3 Functions BOR [ Syntax ] BOR src [ Operation ] C src C [ Function ] • This instruction logically ORs the C flag and src • When is the address register (A0, A1), you can specify the ...
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Chapter 3 Functions BRK [ Syntax ] BRK [ Operation ] • When anything other than FF dress FFFFE7 M(SP) FLG M(SP)* ( M(SP) ( M(FFFFE4 ...
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Chapter 3 Functions BRK2 [ Syntax ] BRK [ Operation ] M(SP) FLG M(SP)* ( M(SP) ( M(0020 ) 16 *1 The ...
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Chapter 3 Functions BSET [ Syntax ] BSET dest [ Operation ] dest 1 [ Function ] • This instruction stores 1 in dest • When is the address register (A0, A1), you can specify the 8 low-order bits for ...
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Chapter 3 Functions BTST [ Syntax ] BTST (:format) src [ Operation ] ______ Z src C src [ Function ] • This instruction transfers inverted src • When is the address register (A0, A1), you can specify the 8 ...
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Chapter 3 Functions BTSTC [ Syntax ] BTSTC dest [ Operation ] ________ Z dest C dest dest 0 [ Function ] • This instruction transfers inverted dest dest • When is the address register (A0, A1), ...
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Chapter 3 Functions BTSTS [ Syntax ] BTSTS dest [ Operation ] ________ Z dest C dest dest 1 [ Function ] • This instruction transfers inverted dest dest • When is the address register (A0, A1), ...
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Chapter 3 Functions BXOR [ Syntax ] BXOR src [ Operation ] A C src C [ Function ] • This instruction exclusive ORs the C flag and src • When is the address register (A0, A1), you can specify ...
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Chapter 3 Functions CLIP [ Syntax ] CLIP.size src1, src2, dest [ Operation ] if src1 > dest then dest src1 if src2 < dest then dest src2 [ Function ] • Signed compares src1 and signed compares src2 and ...
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Chapter 3 Functions CMP [ Syntax ] CMP.size (:format) [ Operation ] dest - src dest - [src] [ Function ] • Each flag bit of the flag register varies depending on the result of subtraction of • When (.B) ...
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Chapter 3 Functions [src/dest Classified by Format format* src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3 A0/A0/A0* A1/A1/A1* [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:24[A0] dsp:24[A1] abs24 #IMM4/#IMM8/#IMM16/#IMM32 *3 Indirect instruction addressing [src] and [dest] can be used ...
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Chapter 3 Functions CMPX [ Syntax ] CMPX src,dest [ Operation ] dest/[dest] - EXTS(src) [ Function ] • Each flag of the flag register changes state according to the result derived by subtracting the sign- src extended 32-bit from ...
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Chapter 3 Functions DADC [ Syntax ] DADC.size src,dest [ Operation ] dest src + dest [ Function ] dest • This instruction adds • When (.W) is specified for the size specifier (.size) and bits become 0. Also, when ...
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Chapter 3 Functions DADD [ Syntax ] DADD.size src,dest [ Operation ] dest src + dest [ Function ] dest • This instruction adds • When (.W) is specified for the size specifier (.size) and bits become 0. Also, when ...
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Chapter 3 Functions DEC [ Syntax ] DEC.size dest [ Operation ] dest dest - 1 [ Function ] • This instruction decrements 1 from • When (.W) is specified for the size specifier (.size) and bits become 0. [ ...
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Chapter 3 Functions DIV [ Syntax ] DIV.size src [ Operation ] • When the size specifier (.size) is (.L) • When the size specifier (.size) is (.W) • When the size specifier (.size) is (.B) [ Function ] • ...
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Chapter 3 Functions DIVU [ Syntax ] DIVU.size src [ Operation ] • When the size specifier (.size) is (.L) • When the size specifier (.size) is (.W) • When the size specifier (.size) is (.B) [ Function ] • ...
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Chapter 3 Functions DIVX [ Syntax ] DIVX.size src [ Operation ] • When the size specifier (.size) is (.L) • When the size specifier (.size) is (.W) • When the size specifier (.size) is (.B) [ Function ] • ...
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Chapter 3 Functions DSBB [ Syntax ] DSBB.size src,dest [ Operation ] dest dest - src - [ Function ] • This instruction subtracts • When (.W) is specified for the size specifier (.size) and bits become 0. Also, when ...
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Chapter 3 Functions DSUB [ Syntax ] DSUB.size src,dest [ Operation ] dest dest - src [ Function ] • This instruction subtracts • When (.W) is specified for the size specifier (.size) and bits become 0. Also, when the ...
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Chapter 3 Functions ENTER [ Syntax ] ENTER src [ Operation ] M(SP M(SP Function ] • This instruction generates a stack frame. src ...
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Chapter 3 Functions EXITD [ Syntax ] EXITD [ Operation ] M(SP M(SP M(SP M(SP Function ] ...
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Chapter 3 Functions EXTS [ Syntax ] EXTS.size dest EXTS.size src,dest [ Operation ] dest EXTS(dest) dest EXTS(src) [ Function ] • This instruction sign extends • When you selected (.B) for the size specifier (.size), is the address register(A0, ...
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Chapter 3 Functions EXTZ [ Syntax ] EXTZ src,dest [ Operation ] dest EXTZ(src) [ Function ] • This instruction zero-extends register(A0, A1), the 8 high-order bits become 0. [ Selectable src/dest ] src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3/- A0/A0/A0 A1/A1/A1 ...
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Chapter 3 Functions FCLR [ Syntax ] FCLR dest [ Operation ] dest 0 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change *1 *1 ...
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Chapter 3 Functions FREIT [ Syntax ] FREIT [ Operation ] FLG SVF PC SVP [ Function ] • Restores the contents of PC and FLG from the high-speed interrupt registers that had been saved when accepting a high-speed interrupt ...
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Chapter 3 Functions FSET [ Syntax ] FSET dest [ Operation ] dest 1 [ Function ] • This instruction stores Selectable dest ] [ Flag Change ] Flag Change *1 *1 ...
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Chapter 3 Functions INC [ Syntax ] INC.size dest [ Operation ] dest dest + 1 [ Function ] • This instruction adds 1 to • When (.W) is specified for the size specifier (.size) and bits become 0. [ ...
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Chapter 3 Functions INDEX Type [ Syntax ] INDEX Type .size [ Operation ] [ Function ] • This instruction modifies addressing of the next instruction. • No interrupts are enabled until after the modifying instruction is executed. • Use ...
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Chapter 3 Functions INT [ Syntax ] INT src [ Operation ] M(SP) FLG M(SP)* ( M(SP) ( M(IntBase [ Function ] • This ...
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Chapter 3 Functions INTO [ Syntax ] INTO [ Operation ] M(SP) FLG M(SP)* ( M(SP) ( M(FFFFE0 [ Function ] • When the ...
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Chapter 3 Functions J Cnd [ Syntax ] J Cnd label [ Operation ] if true then jump label [ Function ] • This instruction causes program flow to branch off after checking the execution result of the preceding instruction ...
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Chapter 3 Functions JMP [ Syntax ] JMP(.length) label [ Operation ] PC label [ Function ] • This instruction causes control to jump to label. [ Selectable label ] .length label . label * ...
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Chapter 3 Functions JMPI [ Syntax ] JMPI.length src [ Operation ] • When jump distance specifier (.length src [ Function ] • This instruction causes control to jump to the address indicated by the address ...
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Chapter 3 Functions JMPS [ Syntax ] JMPS src [ Operation ] FFFE Function ] • This instruction causes control to jump to the address set in each table of the ...
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Chapter 3 Functions JSR [ Syntax ] JSR(.length) label [ Operation ] M(SP)* ( M(SP) (PC PC label *1 The 8 high-oreder bits become denotes the number of bytes in ...
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Chapter 3 Functions JSRI [ Syntax ] JSRI.length src [ Operation ] When jump distance specifier (.length M(SP)* ( M(SP) ( The 8 high-oreder ...
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Chapter 3 Functions JSRS [ Syntax ] JSRS src [ Operation ] M(SP)* ( M(SP) ( FFFE ML *1 The 8 high-oreder bits ...
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Chapter 3 Functions LDC [ Syntax ] LDC src,dest [ Operation ] dest src [ Function ] • This instruction transfers • When memory is specified for 1 2 bytes : DMD0* , DMD1 bytes* : FB, SB, ...
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Chapter 3 Functions LDCTX [ Syntax ] LDCTX abs16,abs24 [ Function ] • This instruction restores task context from the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table ...
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Chapter 3 Functions LDIPL [ Syntax ] LDIPL src [ Operation ] IPL src [ Function ] • This instruction transfers [ Selectable src ] src *1 #IMM3 *1 The range of values is 0 < #IMM3 < ...
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Chapter 3 Functions MAX [ Syntax ] MAX.size src,dest [ Operation ] if (src > dest) then dest src [ Function ] src • Singed compares and src occurs when is smaller than or equal to • When (.W) is ...
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Chapter 3 Functions MIN [ Syntax ] MIN.size src,dest [ Operation ] if (src < dest) then dest src [ Function ] src • Signed compares and src occurs when is greater than or equal to • When (.W) is ...
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Chapter 3 Functions MOV [ Syntax ] MOV.size (:format) src,dest [ Operation ] dest src dest [src] [ Function ] • This instruction transfers • When (.B) is specified for the size specifier (.size) and extended to be treated as ...
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Chapter 3 Functions [src/dest Classified by Format format * src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3/- A0/A0/A0* 5 A1/A1/A1* 5 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:24[A0] dsp:24[A1] abs24 #IMM8/#IMM16/#IMM32 dsp:8[SP]* *4 Indirect instruction addressing [src] and [dest] can ...
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Chapter 3 Functions MOVA [ Syntax ] MOVA src,dest [ Operation ] dest EVA(src) [ Function ] • This instruction transfers the affective address of [ Selectable src/dest ] src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3/- A0/A0/A0 A1/A1/A1 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] ...
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Chapter 3 Functions MOV Dir [ Syntax ] MOV Dir src,dest [ Operation ] Dir Operation HH H4:dest H4:src HL L4:dest H4:src LH H4:dest L4:src LL L4:dest L4:src [ Function ] • Be sure to choose R0L for either Dir ...
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Chapter 3 Functions MOVX [ Syntax ] MOVX src,dest [ Operation ] dest/[dest] EXTS(src) [ Function ] • Sign-extends the 8-bit immediate to 32 bits before transferring it to dest • When is the address register (A0, A1), the 24 ...
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Chapter 3 Functions MUL [ Syntax ] MUL.size src,dest [ Operation ] dest dest src dest dest [src] [ Function ] • This instruction multiplies • When you selected (.B) for the size specifier (.size), operation and the result is ...
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Chapter 3 Functions MULEX [ Syntax ] MULEX src [ Operation ] R1R2R0 R2R0 src/[src] [ Function ] src • Multiplies (16-bit data) and R2R0 including the sign and stores the result in R1R2R0. [ Selectable src] src* 1 R0L/R0/R2R0 ...
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Chapter 3 Functions MULU [ Syntax ] MULU.size src,dest [ Operation ] dest dest src dest dest [src] [ Function ] • This instruction multiplies • When you selected (.B) for the size specifier (.size), operation and the result is ...
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Chapter 3 Functions NEG [ Syntax ] NEG.size dest [ Operation ] dest 0 - dest [ Function ] • This instruction takes the 2's complement of • When (.W) is specified for the size specifier (.size) and high-order bits ...
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Chapter 3 Functions NOP [ Syntax ] NOP [ Operation ] Function ] • This instruction adds 1 to PC. [ Flag Change ] Flag Change [ Description Example ] ...
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Chapter 3 Functions NOT [ Syntax ] NOT.size dest [ Operation ] dest dest [ Function ] dest • This instruction inverts • When (.W) is specified for the size specifier (.size) and order bits become 0. [ Selectable dest ...
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Chapter 3 Functions OR [ Syntax ] OR.size (:format) src,dest [ Operation ] dest src dest dest [src] dest [ Function ] • This instruction logically ORs • When (.B) is specified for the size specifier (.size) and extended to ...
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Chapter 3 Functions [src/dest Classified by Format format* src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3 A0/A0/A0* A1/A1/A1* [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB] dsp:24[A0] dsp:24[A1] abs24 #IMM8/#IMM16 *3 Indirect instruction addressing [src] and [dest] can be ...
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Chapter 3 Functions POP [ Syntax ] POP.size dest [ Operation ] dest/[dest] M(SP Even when (.B) is specified for the size specifier (.size increased Function ] • This instruction restores ...
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Chapter 3 Functions POPC [ Syntax ] POPC dest [ Operation ] • When dest is DCT0, DCT1, DMD0, DMD1, DRC0, DRC1, SVF or FLG dest* 1 M(SP The 8 low-order bytes are saved when ...
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Chapter 3 Functions POPM [ Syntax ] POPM dest [ Operation ] dest* 3 M( denotes the number of R0, R1, R2 and R3 registers to be restored ...
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Chapter 3 Functions PUSH [ Syntax ] PUSH.size src [ Operation ] • When the size specifier (.size M(SP)* 1 src/[src] *1 The 8 high-order bits become undefined. Even when (.B) is specified for ...
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Chapter 3 Functions PUSHA [ Syntax ] PUSHA src [ Operation ] M(SP)* EVA(src) *1 The 8 high-order bits become undefined. [ Function ] • This instruction saves the effective address of [ Selectable src ...
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Chapter 3 Functions PUSHC [ Syntax ] PUSHC src [ Operation ] src • When is DCT0, DCT1, DMD0, DMD1, DRC0, DRC1, SVF or FLG M(SP)* src src *1 When is DMD0 or DMD1, the ...
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Chapter 3 Functions PUSHM [ Syntax ] PUSHM src [ Operation ] SP SP – n1 – n2* 3 M(SP)* src *1 n1 denotes the number of R0, R1, R2 and R3 registers to be saved ...
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Chapter 3 Functions REIT [ Syntax ] REIT [ Operation ] PC M(SP M(SP FLG M(SP The 8 high-order bits are saved. [ Function ] • This ...
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Chapter 3 Functions RMPA [ Syntax ] RMPA.size *1 [ Operation ] Repeat R1R2R0 Until When you set a value 0 in R3, this instruction is ingored. *2 Shown ...
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Chapter 3 Functions ROLC [ Syntax ] ROLC.size dest [ Operation ] [ Function ] dest • This instruction rotates • When (.W) is specified for the size specifier (.size) and high-order bits become 0. [ Selectable dest ] *1 ...
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Chapter 3 Functions RORC [ Syntax ] RORC.size dest [ Operation ] [ Function ] dest • This instruction rotates • When (.W) is specified for the size specifier (.size) and high-order bits become 0. [ Selectable dest ] *1 ...
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Chapter 3 Functions ROT [ Syntax ] ROT.size src,dest [ Operation ] C [ Function ] dest • This instruction rotates (MSB) is transferred to MSB(LSB) and the C flag. • The direction of rotate is determined by the sign ...
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Chapter 3 Functions RTS [ Syntax ] RTS [ Operation ] PC M(SP M(SP The 8 low-order bits are saved. [ Function ] • This instruction causes ...
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Chapter 3 Functions SBB [ Syntax ] SBB.size src,dest [ Operation ] dest dest - src - [ Function ] • This instruction subtracts • When (.B) is specified for the size specifier (.size) and extended to be treated as ...
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Chapter 3 Functions SBJNZ [ Syntax ] SBJNZ.size src,dest,label [ Operation ] dest dest - src if dest 0 then jump label [ Function ] • This instruction subtracts • When the operation resulted in any value other than 0, ...
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Chapter 3 Functions SC Cnd [ Syntax ] SC Cnd label [ Operation ] if true then dest else dest [ Function ] • When the condition specified by dest false, it stores dest • When is ...
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Chapter 3 Functions SCMPU [ Syntax ] SCMPU.size [ Operation ] • When the size specifier (.size) is (.B) Repeat M(A0) – M(A1) (compared by byte) tmp0 M(A0) tmp2 M(A1 Until (tmp0=0) ...
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Chapter 3 Functions SHA [ Syntax ] SHA.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction arithmetically shifts flowing from LSB(MSB)is transferred to the C flag. • The direction of ...
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Chapter 3 Functions SHANC [ Syntax ] SHANC.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction arithmetically shifts • The direction of shift is determined by the sign of negative, ...
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Chapter 3 Functions SHL [ Syntax ] SHL.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction logically shifts from LSB (MSB) is transferred to the C flag. • The direction ...
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Chapter 3 Functions SHLNC [ Syntax ] SHLNC.size src,dest [ Operation ] src When < 0 src When > Function ] • This instruction logically shifts • The direction of shift is determined by the sign of negative, ...
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Chapter 3 Functions SIN [ Syntax ] SIN.size *1 [ Operation ] • When size specifier (.size) is (.B) While M(A1) M(A0 End *1 When you set a value 0 in ...
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Chapter 3 Functions SMOVB [ Syntax ] SMOVB.size *1 [ Operation ] • When size specifier (.size) is (.B) While M(A1) M(A0 End *1 When you set a ...
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Chapter 3 Functions SMOVF [ Syntax ] SMOVF.size *1 [ Operation ] • When size specifier (.size) is (.B) While M(A1) M(A0 End *1 When you set a ...
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Chapter 3 Functions SMOVU [ Syntax ] SMOVU.size [ Operation ] • When size specifier (.size) is (.B) Repeat M(A1) M(A0) (transfered by byte) tmp0 M(A0 Until tmp0 = 0 tmp0: temporary register ...
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Chapter 3 Functions SOUT [ Syntax ] SOUT.size *1 [ Operation ] • When size specifier (.size) is (.B) While M(A1) M(A0 End *1 When you set a value 0 in ...
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Chapter 3 Functions SSTR [ Syntax ] SSTR.size *1 [ Operation ] • When size specifier (.size) is (.B) While M(A1) R0L End *1 When you set a value 0 in ...
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Chapter 3 Functions STC [ Syntax ] STC src,dest [ Operation ] dest src [ Function ] • This instruction transfers the control register indicated by the address in which to store the low-order address. • When memory is specified ...
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Chapter 3 Functions STCTX [ Syntax ] STCTX abs16,abs24 [ Operation ] [ Function ] • This instruction saves task context to the stack area. • Set the RAM address that contains the task number in abs16 and the start ...
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Chapter 3 Functions STNZ [ Syntax ] STNZ.size src,dest [ Operation ] then dest/[dest] [ Function ] • This instruction transfers • When (.B) is specified for the size specifier (.size) and extended to be treated ...
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Chapter 3 Functions STZ [ Syntax ] STZ.size src,dest [ Operation ] then dest/[dest] [ Function ] • This instruction transfers • When (.B) is specified for the size specifier (.size) and extended to be treated ...
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Chapter 3 Functions STZX [ Syntax ] STZX.size src1,src2,dest [ Operation ] then dest src1 else dest src2 [ Function ] • This instruction transfers dest . • When (.B) is specified for the size specifier ...
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Chapter 3 Functions SUB [ Syntax ] SUB.size (:format) [ Operation ] dest dest - src dest dest - [src] [ Function ] • This instruction subtracts • When (.B) is specified for the size specifier (.size) and extended to ...
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Chapter 3 Functions [ Description Example ] SUB.B A0,R0L SUB.B R0L,A0 SUB.B Ram:8[SB],R0L SUB.W #2,[A0] [src/dest Classified by Format format* src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3/- A0/A0/A0* 4 A1/A1/A1* 4 [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:24[A0] dsp:24[A1] ...
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Chapter 3 Functions SUBX [ Syntax ] SUBX src,dest [ Operation ] dest dest - EXT(src) dest dest - EXT([src]) [ Function ] • This instruction subtracts 8-bit dest result in . dest • When is the address register (A0, ...
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Chapter 3 Functions TST [ Syntax ] TST.size(:format) [ Operation ] dest src [ Function ] • Each flag in the flag register changes state depending on the result of logical AND of • When (.B) is specified for the ...
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Chapter 3 Functions [src/dest Classified by Format] G format src R0L/R0/R2R0 R0H/R2/- R1L/R1/R3R1 R1H/R3 A0/A0/A0* A1/A1/A1* [A0] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:24[A0] dsp:24[A1] abs24 #IMM8/#IMM16 *2 When you specify (.B) for the size specifier (.size), you ...
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Chapter 3 Functions UND [ Syntax ] UND [ Operation ] M(SP) FLG M(SP)* ( M(SP) (PC PC M(FFFFDC *1 The 8 high-order bits become undefined. [ Function ] • ...
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Chapter 3 Functions WAIT [ Syntax ] WAIT [ Operation ] [ Function ] • Stops program execution. Program execution is restarted when an interrupt whose priority level is higher than bits RLVL2 to RLVL0 in the RLVL register is ...
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Chapter 3 Functions XCHG [ Syntax ] XCHG.size src,dest [ Operation ] dest/[dest] src [ Function ] • This instruction exchanges contents between • When (.B) is specified for the size specifier (.size) and src expanded data are placed in ...
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Chapter 3 Functions XOR [ Syntax ] XOR.size src,dest [ Operation ] dest dest src dest dest [src] [ Function ] • This instruction exclusive ORs • When (.B) is specified for the size specifier (.size) and extended to be ...
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Chapter 3 Functions 3.3 Index instructions This section explains each INDEX instruction individually. The INDEX instructions are provided for use on arrays. The effective addresses are derived by unsigned adding the addresses indicated by src and dest of the next ...
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Chapter 3 Functions (2) INDEXBD.size The INDEXBD (INDEX Byte Dest) instruction is used for arrays arranged in bytes. The effective addresses for the INDEXBD instruction are derived by unsigned adding the src content of the INDEXBD instruction to the addresses ...
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Chapter 3 Functions (3) INDEXBS.size The INDEXBS (INDEX Byte Src) instruction is used for arrays arranged in bytes. The effective addresses for the INDEXBS instruction are derived by unsigned adding the src content of the INDEXBS instruction to the addresses ...
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Chapter 3 Functions (4)INDEXW.size src The INDEXW (INDEX Word) is used for arrays arranged in words. The effective addresses for the INDEXW instruction are derived by unsigned adding twice the src con- tent of the INDEXW instruction to the addresses ...
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Chapter 3 Functions (5) INDEXWD.size The INDEXWD (INDEX Word Dest) is used for arrays arranged in words. The effective addresses for the INDEXWD instruction are derived by unsigned adding twice the src content of the INDEXWD instruction to the addresses ...
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Chapter 3 Functions (6) INDEXWS.size The INDEXWS (INDEX Word Src) is used for arrays arranged in words. The effective addresses for the INDEXWS instruction are derived by unsigned adding twice the src content of the INDEXWS instruction to the addresses ...
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Chapter 3 Functions (7) INDEXL.size src The INDEXL (INDEX Long word) is used for arrays arranged in long words. The effective addresses for the INDEXL instruction are derived by unsigned adding four times the src content of the INDEXL instruction ...
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Chapter 3 Functions (8) INDEXLD.size The INDEXLD (INDEX Long word Dest) is used for arrays arranged in long words. The effective addresses for the INDEXLD instruction are derived by unsigned adding four times the src content of the INDEXLD instruction ...
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Chapter 3 Functions (9) INDEXLS.size The INDEXLS (INDEX Long word Src) is used for arrays arranged in long words. The effective addresses for the INDEXLS instruction are derived by unsigned adding four times the src content of the INDEXLS instruction ...
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Chapter 3 Functions (10) BITINDEX.size The BITINDEX instruction is operated on the bit that is apart from bit 0 of the address indicated by dest as many bits as indicated by src of BITINDEX. Make sure the next instruction to ...
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Chapter 3 Functions (11) Next instructions that can be executed after INDEX The table below lists the next instructions that can be executed after each INDEX instruction. INDEXB.B/.W* 2 ADC, ADD:G* MULU, OR, SBB, SUB,TST,XOR The src and dest of ...
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Chapter 3 Functions (12) Addressing modes The table below lists the addressing modes that become valid in the next instructions that can be ex- ecuted after INDEX. Indirect instruction addressing modes can be used in each instruction. src [A0] [A1] ...
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Chapter 3 Functions 170 ...
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Instruction Code/Number of Cycles Chapter 4 4.1 Guide to This Chapter 4.2 Instruction Code/Number of Cycles ...
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Chapter 4 Instruction Code 4.1 Guide to This Chapter This chapter describes instruction code and number of cycles for each op-code. The following shows how to read this chapter by using an actual page as an example. Chapter 4 Instruction ...
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Chapter 4 Instruction Code (1) Mnemonic Shows the mnemonic explained in this page. (2) Syntax Shows an instruction syntax using symbols. (3) Instruction code Shows instruction code. Entered are omitted depending on src/dest you selected. Content at ...
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Chapter 4 Instruction Code/Number of Cycles 4.2 Instruction Code/Number of Cycles ABS (1) ABS.size dest SIZE When dest is indirectly addressed the code has 00001001 added ...
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Chapter 4 Instruction Code/Number of Cycles (2) ADC.size src, dest 0000 0001 SIZE .size SIZE src/dest . [An] dsp:8[An] [ ...
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Chapter 4 Instruction Code/Number of Cycles ADCF (1) ADCF.size dest SIZE When dest is indirectly addressed the code has 00001001 added at the beginning. .size SIZE ...
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Chapter 4 Instruction Code/Number of Cycles (2) ADD.L:G #IMM,dest When dest is indirectly addressed the code has 00001001 added at the beginning. dest ---/---/R2R0 ---/---/R3R1 ...
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Chapter 4 Instruction Code/Number of Cycles ADD (3) ADD.size:Q #IMM, dest SIZE1 SIZE2 When dest is indirectly addressed the code has 00001001 added at the beginning. .size ...
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Chapter 4 Instruction Code/Number of Cycles (4) ADD.size:S #IMM, dest SIZE *1 When dest is indirectly addressed the code has 00001001 added at the beginning. .size SIZE dest . ...
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Chapter 4 Instruction Code/Number of Cycles ADD (6) ADD.size:G src, dest SIZE For indirect instruction addressing, the following number is added at the beginning ...
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Chapter 4 Instruction Code/Number of Cycles (7) ADD.L:G src, dest For indirect instruction addressing, the following number is added at the beginning of ...
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Chapter 4 Instruction Code/Number of Cycles ADD (8) ADD.L:G #IMM16 Number of Bytes/Number of Cycles ] Bytes/Cycles 4/2 ADD (9) ADD.L:Q #IMM3 ...