M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 68

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
AND
[ Syntax ]
[ Operation ]
[ Function ]
[ Flag Change ]
[ Description Example ]
[ Selectable src/dest ] *
J
Chapter 3
*1 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-,
*2 When you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
Change
1 .
0
R0L/R0/R2R0
R1L/R1/R2R0
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16
Conditions
Flag
9
AND.size (:format)
dest
dest
0 .
B
• This instruction logically ANDs
• When (.B) is specified for the size specifier (.size) and
• When (.W) is specified for the size specifier (.size) and
R1L/R1/R3R1, R1H/R3/-, and #IMM.
simultaneously.
S :
Z :
AND.B
AND.B:G
AND.B:G
AND.B:S
AND.W:G
0
0
extended to be treated as 16-bit data for the operation. In this case, the 8 high-oreder bits become 0.
Also, when
be operated on.
bits become 0. Also, when
the data to be operated on.
3
1
2
9
0
U
0 -
0
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
6
1
2
0 .
0
0
src
[src]
5
I
3 .
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
Functions
1
Ram:8[SB],R0L
A0,R0L
R0L,A0
#3,R0L
[A0],[[A1]]
src
O
p
a
is the address register, the 8 low-order bits of the address register are used as data to
g
B
e
dest
dest
1
src
2
50
S
abs24
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB] dsp:16[FB]
src,dest
f o
Z
3
src
3
5
[dest]
[dest]
D
is the address register, the 16 low-order bits of the address register are
dest
C
[A1]
dsp:8[FB]
abs16
and
G , S (Can be specified)
B , W
Logically AND
src
[src]
src
together and stores the result in
(See the next page for
AND
R0L/R0/R2R0
R1L/R1/R2R0
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
; A0's 8 low-order bits and R0L are ANDed.
; R0L is zero-expanded and ANDed with A0.
[dest]
[dest]
dest
dest
is the address register (A0, A1),
2
[ Instruction Code/Number of Cycles ]
is the address register, the 8 high-order
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
src
/
dest
dest
2
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB] dsp:16[FB]
abs24
classified by format.)
dest
.
3.2
src
abs16
[A1]
dsp:8[FB]
AND
src
Functions
Page= 186
and
is zero-
dest