M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 348

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Chapter 6
Figure 6.1.8. When executing a read instruction for memory connected to 8-bit bus
1 .
0
9
Data bus (H)
Data bus (L)
0 .
Address bus
Fetch code
Instructions
under execution
Instruction
queue buffer
Content at jump address
is prefetched at the
same time the instruction
queue buffer is cleared.
B
BCLK
RD
WR
0
0
3
1
2
9
0
0 -
0
6
1
0 .
0
0
5
3 .
(Program area: 8-bit bus without wait state; Data area: 8-bit bus without wait state)
Jump address
Calculation number of cycles
FFC027 FFC02C FFC02D FFC02E FFC02F
1
DR : Indicates a data read.
7A
DE
DE
DE
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
Sample program
Address
FFC024
FFC024
FFC025
FFC026
FFC027
FFC028
FFC029
FFC02A
FFC02B
FFC02C
FFC02C
FFC030
FFC031
FFC032
FFC033
FFC034
FFC035
FFC036
FFC037
FFC038
p
: Indicates the locations of the instruction queue buffer that are cleared.
DE
P
a
g
JMP TEST_11
e
B9
330
B9
P
7A
DE
DE
DE
DE
DE
DE
DE
B9FB0080
7A
DE
DE
DE
DE
DE
DE
DE
Code
FB
B9
f o
TEST_10:
TEST_11:
TEST_12:
FB
P
3
3
5
FB
B9
00
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W:G
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
00
P
Fetch
B9FB
00
80
80
P
FFC030
7A
00
80
TEST_11
08000h,R1
TEST_12
Content at address 8000
7A
P
FFC031 08000
DE
00
80
7A
DE
P
MOV.W
Fetch
0080
DE
7A
DR
AA
08001 FFC032
DE
7A
16
DR
AA
Content at address 8001
DE
DE
7A
DE
P
Fetch
FFC033 FFC038 FFC039 FFC03A
DE
DE
DE
7A
DE
P
6.1 Instruction queue buffer
JMP TEST_12
B9
P
B9
Content at jump address
is prefetched at the
same time the instruction
queue buffer is cleared.
16
B9
FB
P
FB
FB
B9
00
P
00