M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 154

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
SHL
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]
[ Flag Change ]*
[ Description Example ]
J
Chapter 3
*1 Indirect instruction addressing [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-,
*2 When
*3 When (.B) or (.W) is selected for the size specifier (.size), the range of values is
1 .
Change
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM4/#IMM8*
Conditions
9
SHL.size
0 .
Flag
• This instruction logically shifts
• The direction of shift is determined by the sign of
• When
• When
B
S*
Z*
C*
*5 When (.L) is specified for the sign specifier (.size) and dest is the address register(A0, A1), the flag
SHL.B
SHL.B
SHL.L
SHL.W
0
R1L/R1/R3R1, and R1H/R3/-.
-8 < #IMM4 < +8( 0). When (.L) is selected for the size specifier (.size), the range of values is -32 <
#IMM8 < +32 ( 0).
0
from LSB (MSB) is transferred to the C flag.
negative, bits are shifted right.
is -8 to +8( 0). You cannot set values less than -8, equal to 0, or greater than +8. When (.L) is
specified for the size specifier (.size), the number of shifts is -32 to +32 ( 0). You cannot set the value
0.
and no flags are changed. When you set a value less than -32 or greater than +32, the result of shift
is undefined.
3
5
5
5
:
:
become undefined.
1
:
2
9
0
0 -
0
U
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
The flag is set when the bit shifted out last is 1; otherwise cleared.
When
When
6
src
1
src
src
0 .
0
0
5
3 .
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
is R1H, you cannot choose R1, R1H or R3R1 for
is an immediate and (.B) or (.W) is specified for the size specifier (.size), the number of shifts
I
is a register, the number of shifts is -32 to +32. Although you can set 0, no bits are shifted
Functions
1
3
#3,R0L
#-3,R0L
R1H,Ram:8[A1]
R1H,[[A0]]
src
src
4
O
p
< 0
> 0
a
g
e
src,dest
B
136
src
S
R0H/R2/-
R1H*
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
f o
3
Z
3
2
/R3/-
5
dest
D
C
0
left or right the number of bits indicated by
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
B , W , L
SHift Logical
*4 When the number of shifts is 0, no flags are changed.
Shift logical
MSB
MSB
R0L/R0/R2R0
R1L/R1/R3R1*
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
src
; Logically shifted left
; Logically shifted right
. When
dest/[dest]
dest/[dest]
dest
src
[ Instruction Code/Number of Cycles ]
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
.
2
is positive, bits are shifted left; when
LSB
LSB
dest*
R0H/R2/-
R1H/R3/-*
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
src
1
. The bit overflowing
C
0
3.2
2
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
Page= 285
Functions
SHL