M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 267

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
Chapter 4
v
(7) MOV.size:G
J
*1 For indirect instruction addressing, the following number is
[ Number of Bytes/Number of Cycles ]
*2 When src or dest is indirectly addressed, the number of bytes and cycles in the table are increased by 1 and 3,
b7
1 .
0
src
Rn
An
[An]
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB/FB] 4/3
dsp:24[An]
abs16
abs24
.size
1
9
.W
.B
0 .
B
added at the beginning of code:
respectively. Also, when src and dest both are indirectly addressed, the number of bytes and cycles in the table are
increased by 1 and 6, respectively.
0
0
s4 s3 s2 d4 d3 d2 SIZE d1 d0 s1 s0 1
3
1
01000001 when src is indirectly addressed
00001001 when dest is indirectly addressed
01001001 when src and dest are indirectly addressed
SIZE
2
9
0
0
1
0 -
0
6
dest Rn
1
0 .
0
0
5
3 .
Instruction Code/Number of Cycles
Rn
An
[An]
dsp:8[An]
1
2/1
2/1
2/3
3/3
3/3
4/3
5/3
4/3
5/3
p
a
g
2/1
2/1
2/3
3/3
3/3
4/3
4/3
5/3
4/3
5/3
An
e
src, dest
b0 b7
249
src/dest
[An] dsp:8[An] dsp:8[SB/FB] dsp:16[An] dsp:16[SB/FB] dsp:24[An] abs16 abs24
2/1
2/1
2/3
3/3
3/3
4/3
4/3
5/3
4/3
5/3
f o
R0L/R0/---
R1L/R1/---
R0H/R2/-
R1H/R3/-
A0
A1
[A0]
[A1]
dsp:8[A0]
dsp:8[A1]
3
3
3/1
3/1
3/2
4/2
4/2
5/2
5/2
6/2
5/2
6/2
5
0
s4 s3 s2 s1 s0
d4 d3 d2 d1 d0
1 0 0 1 0
1 0 0 1 1
1 0 0 0 0
1 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 0 0 0
0 0 0 0 1
0 0 1 0 0
0 0 1 0 1
3/1
3/1
3/2
4/2
4/2
5/2
5/2
6/2
5/2
6/2
1
b0
1
(
4/1
4/1
4/2
5/2
5/2
6/2
6/2
7/2
6/2
7/2
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB/FB]
dsp:24[An]
abs16
abs24
dsp8
dsp16/abs16
4.2
dsp24/abs24
src code
Instruction Code/Number of Cycles
src/dest
4/1
4/1
4/2
5/2
5/2
6/2
6/2
7/2
6/2
7/2
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
dsp:16[FB]
dsp:24[A0]
dsp:24[A1]
abs16
abs24
)
(
5/1
5/1
5/2
6/2
6/2
7/2
7/2
8/2
7/2
8/2
dsp8
dsp16/abs16
dsp24/abs24
dest code
s4 s3 s2 s1 s0
d4 d3 d2 d1 d0
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 1
0 1 1 1 0
4/2
6/2
6/2
7/2
4/1
4/1
5/2
5/2
6/2
7/2
MOV
5/1
5/1
5/2
6/2
6/2
7/2
7/2
8/2
7/2
8/2
)