M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 94

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
[ Function ]
[ Selectable src ]
[ Flag Change ]
[ Description Example ]
DIV
[ Syntax ]
v
[ Operation ]
Conditions
J
Chapter 3
*1 When (.B) and (.W) are specified for the size specifier (.size), indirect instruction addressing [src] can
Change
1 .
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16/#IMM32
0
Flag
9
DIV.size
• When the size specifier (.size) is (.L)
• When the size specifier (.size) is (.W)
• When the size specifier (.size) is (.B)
0 .
O :
B
• When (.B) is specified for the size specifier (.size), this instruction divides R0 by signed
• When (.W) is specified for the size specifier (.size), this instruction divides R2R0 by signed
• When (.L) is specified for the size specifier (.size), this instruction divides R2R0 by signed
DIV.B
DIV.B
DIV.W
DIV.W
DIV.L
be used in all addressing except R0L/R0/-, R0H/R2/-, R1L/R1/-, R1/-, R1H/R3/-, and #IMM. When
(.size) is (.L), indirect instruction addressing [src] cannot be used.
0
0
the quotient in R0L and the remainder in R0H. The remainder's sign is the same as the dividend's sign.
When
to be operated on. The O flag is set when the operation resulted in the quotient exceeding 8 bits or the
divider is 0. R0L and R0H is undefined.
stores the quotient in R0 and the remainder in R2. The remainder's sign is the same as the divider's
sign. When
to be operated on. The O flag is set when the operation resulted in the quotient exceeding 16 bits or
the divider is 0. R0 and R2 is undefined.
the quotient in R2R0. The remainder is not operated, but the remainder's sign is the same as the
divider's sign. When
operation. The O flag is set when the divider is 0. R2R0 is undefined.
3
1
2
9
0
The flag is set when the operation resulted in the quotient exceeding 16 bits (.W), 8 bits (.B) or the
divider is 0; otherwise cleared.
U
0 -
0
6
1
0 .
src
0
0
5
I
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
3 .
is the address register (A0, A1), the 8 low-order bits of the address register are used as data
Functions
1
src
A0
#4
R0
[[A1]]
R3R1
src
O
p
a
is the address register, the 16 low-order bits of the address register are used as data
g
B
e
src*
76
src
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
1
is the address register,
f o
Z
3
3
5
D
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
B , W , L
Signed divide
R2R0 (quotient)
R0 (quotient), R2 (remainder)
R0L (quotient), R0H (remainder)
DIVide
src
is zero-extended to be treated as 32-bit data for the
;A0's 8 low-order bits is the divider.
;The remainder is not operated.
[ Instruction Code/Number of Cycles ]
R2R0
src
R2R0
R0
src/[src]
src/[src]
3.2 Functions
src
src
and stores
and stores
Page= 210
DIV
src
and