M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 170

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
[ Flag Change ]
[ Selectable src/dest ]
v
TST
[ Syntax ]
[ Operation ]
[ Function ]
[ Description Example ]
J
*1 When you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
Chapter 3
Change
1 .
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16
Conditions
0
Flag
9
TST.size(:format)
dest
0 .
B
S :
Z :
• Each flag in the flag register changes state depending on the result of logical AND of
• When (.B) is specified for the size specifier (.size) and
• When (.W) is specified for the size specifier (.size) and
TST.B
TST.B
TST.B
simultaneously.
0
0
extended to be treated as 16-bit data for the operation. Also, when
low-order bits of the address register are used as data to be operated on.
of the address register are the data to be operated on.
3
1
2
9
0
U
0 -
0
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
6
1
1
0 .
0
src
0
5
I
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
3 .
Functions
1
#3,R0L
A0,R0L
R0L,A0
O
p
a
g
e
B
src
1
152
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
src,dest
f o
Z
3
3
5
D
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
G , S (Can be specified)
B , W
; A0's 8 low-order bits and R0L are operated on.
; R0L is zero-expanded and operated on with A0.
TeST
Test
(See the next page for
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
dest
src
is the address register, the 16 low-order bits
is the address register (A0, A1),
1
[ Instruction Code/Number of Cycles ]
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
src
src/dest
dest
is the address register, the 8
1
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
classified by format.)
3.2
src
src
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
and
src
Page=
Functions
TST
and
is zero-
dest
dest
301
.