M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet
M30853FJGP#U3
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M30853FJGP#U3 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M32C/85 Group 16/ (M32C/85, M32C/85T) 32 Hardware Manual RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is ...
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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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Introduction This hardware manual provides detailed information on the M32C/85 group (M32C/85, M32C/85T) microcom- puters. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit ...
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M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : ...
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Table of Contents Quick Reference by Address _____________________ B-1 1. Overview _____________________________________ 1 1.1 Applications ................................................................................................................ 1 1.2 Performance Overview .............................................................................................. 2 1.3 Block Diagram ............................................................................................................ 4 1.4 Product Information ................................................................................................... 5 1.5 Pin Assignments and Descriptions .......................................................................... 7 1.6 ...
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Processor Mode ______________________________ 57 7.1 Types of Processor Mode ........................................................................................ 57 7.2 Setting of Processor Mode ...................................................................................... 58 8. Bus_________________________________________ 62 8.1 Bus Settings ............................................................................................................. 62 8.1.1 Selecting External Address Bus ...................................................................... 63 8.1.2 Selecting External Data Bus ............................................................................ ...
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Protection _________________________________ 104 11. Interrupts __________________________________ 105 11.1 Types of Interrupts ............................................................................................... 105 11.2 Software Interrupts .............................................................................................. 106 11.2.1 Undefined Instruction Interrupt ................................................................... 106 11.2.2 Overflow Interrupt ......................................................................................... 106 11.2.3 BRK Interrupt ................................................................................................. 106 11.2.4 BRK2 Interrupt ............................................................................................... 106 ...
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DMAC_____________________________________ 133 13.1 Transfer Cycle ...................................................................................................... 140 13.1.1 Effect of Source and Destination Addresses ............................................. 140 13.1.2 Effect of the DS Register .............................................................................. 140 13.1.3 Effect of Software Wait State ....................................................................... 140 ________ 13.1.4 Effect of RDY Signal ..................................................................................... ...
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Three-Phase Motor Control Timer Functions ____ 180 17. Serial I/O __________________________________ 191 17.1 Clock Synchronous Serial I/O Mode .................................................................. 201 17.1.1 Selecting CLK Polarity Selecting ................................................................ 205 17.1.2 Selecting LSB First or MSB First ................................................................. 205 17.1.3 Continuous Receive ...
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Functions .............................................................................................................. 259 18.2.1 Resolution Select Function .......................................................................... 259 18.2.2 Sample and Hold Function ........................................................................... 259 18.2.3 Trigger Select Function ................................................................................ 259 18.2.4 DMAC Operating Mode ................................................................................. 259 18.2.5 Extended Analog Input Pins ........................................................................ 260 18.2.6 External Operating Amplifier ...
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CANi Slot Interrupt Mask Register (CiSIMKR Register) (i=0, 1) .............. 338 23.1.13 CANi Error Interrupt Mask Register (CiEIMKR Register) (i=0, 1) ............ 339 23.1.14 CANi Error Interrupt Status Register (CiEISTR Register) (i=0, 1) ........... 340 23.1.15 CANi Error Factor ...
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Functions to Prevent the Flash Memory from Rewriting ................................. 396 25.2.1 ROM Code Protect Function ........................................................................ 396 25.2.2 ID Code Verify Function ............................................................................... 396 25.3 CPU Rewrite Mode ............................................................................................... 398 25.3.1 EW Mode 0 ..................................................................................................... 398 25.3.2 EW Mode ...
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Interrupts .............................................................................................................. 475 27.7.1 ISP Setting ..................................................................................................... 475 _______ 27.7.2 NMI Interrupt .................................................................................................. 475 ______ 27.7.3 INT Interrupt .................................................................................................. 475 27.7.4 Watchdog Timer Interrupt ............................................................................ 476 27.7.5 Changing Interrupt Control Register .......................................................... 476 27.7.6 Changing IIOiIR Register (i = ...
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Quick Reference by Address Quick Reference by Address Address Register 0000 16 0001 16 0002 16 0003 16 0004 Processor Mode Register 0 (PM0) 16 0005 Processor Mode Register 1 (PM1) 16 0006 System Clock Control Register 0 (CM0) 16 ...
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Quick Reference by Address Address Register 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 DMA0 Interrupt Control Register (DM0IC) 16 0069 Timer B5 Interrupt Control Register (TB5IC) 16 006A DMA2 Interrupt ...
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Quick Reference by Address Address Register 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 ...
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Quick Reference by Address Address Register 0120 16 Base Timer Register1 (G1BT) 0121 16 0122 Base Timer Control Register 10 (G1BCR0) 16 0123 Base Timer Control Register 11 (G1BCR1) 16 0124 Time Measurement Prescaler Register 16 (G1TPR6) 16 0125 Time ...
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Quick Reference by Address Address Register 01E0 CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0) 16 01E1 CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1) 16 01E2 CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2) 16 01E3 CAN0 Message Slot ...
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Quick Reference by Address Address Register CAN0 Message Slot 9 Control Register (C0MCTL9)/ 0239 16 CAN0 Local Mask Register B Standard ID1 (C0LMBR1) CAN0 Message Slot 10 Control Register (C0MCTL10)/ 353/ 023A 16 CAN0 Local Mask Register B Extended ID0 ...
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Quick Reference by Address Address Register 0290 16 CAN1 Slot Interrupt Mask Register (C1SIMKR) 0291 16 0292 16 0293 16 0294 CAN1 Error Interrupt Mask Register (C1EIMKR) 16 0295 CAN1 Error Interrupt Status Register (C1EISTR) 16 0296 CAN1 Error Factor ...
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Quick Reference by Address Address Register 02E0 X/Y Control Register (XYC) 16 02E1 16 02E2 16 02E3 16 02E4 UART1 Special Mode Register 4 (U1SMR4) 16 02E5 UART1 Special Mode Register 3 (U1SMR3) 16 02E6 UART1 Special Mode Register 2 ...
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Quick Reference by Address Address Register 0340 Count Start Flag (TABSR) 16 0341 Clock Prescaler Reset Flag (CPSRF) 16 0342 One-Shot Start Flag (ONSF) 16 0343 Trigger Select Register (TRGSR) 16 0344 Up-Down Flag (UDF) 16 0345 16 0346 16 ...
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Quick Reference by Address Address Register 03A0 Function Select Register A8 (PS8) 16 03A1 Function Select Register A9 (PS9) 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 Function Select Register D1 (PSD1) 16 03A8 16 03A9 ...
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M32C/85 Group (M32C/85, M32C/85T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/85 group (M32C/85, M32C/85T) microcomputer is a single-chip control unit that utilizes high- performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/85 group (M32C/85, M32C/85T) ...
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1.2 Performance Overview Tables 1.1 and 1.2 list performance overview of the M32C/85 group (M32C/85, M32C/85T). ...
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Table 1.2 M32C/85 Group (M32C/85, M32C/85T) Performance (100-Pin Package) Characteristic CPU Basic Instructions Minimum Instruction Execution ...
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1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/85 group (M32C/85, M32C/85T) microcomputer. ...
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1.4 Product Information Table 1.3 lists the product information. Figure 1.2 shows the product numbering system. ...
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M30 Figure 1.2 Product Numbering System Page ...
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1.5 Pin Assignments and Descriptions Figures 1.3 to 1.5 show pin assignments (top view ...
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Table 1.4 Pin Characteristics for 144-Pin Package Pin Interrupt Control Port No. Pin Pin P9 1 ...
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Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin Control Interrupt Port No. Pin Pin 49 ...
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Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin Control Interrupt Port Timer Pin No. Pin ...
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...
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AN0 / AN0 / ...
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Table 1.5 Pin Characteristics for 100-Pin Package Package Control Interrupt Pin No. Port Pin Pin FP ...
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Table 1.5 Pin Characteristics for 100-Pin Package (Continued) Package Control Interrupt Pin No. Port Pin Pin ...
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1.6 Pin Description Table 1.6 Pin Description (100-Pin and 144-Pin Packages) Classsfication Symbol I/O Type Power ...
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Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol I/O Type Main Clock Input ...
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Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol I/O Type V Reference REF ...
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Table 1.6 Pin Description (144-Pin Package only) (Continued) Classsfication Symbol I/O Type A/D Converter AN15 to ...
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Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised ...
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2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 ...
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2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag ...
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Memory Figure 3.1 shows a memory map of the M32C/85 group (M32C/85, M32C/85T). The M32C/85 ...
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Special Function Registers (SFR) Address 0000 16 0001 16 0002 16 0003 16 0004 Processor ...
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Address Register 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 ...
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Address 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 ...
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Address 0090 UART0 Transmit /NACK Interrupt Control Register 16 0091 UART1/UART4 Bus Conflict Detect Interrupt Control ...
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Address 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 ...
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Address 00F0 Data Compare Register 00 16 00F1 Data Compare Register 01 16 00F2 Data Compare ...
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Address 0120 16 Base Timer Register 1 0121 16 0122 Base Timer Control Register 10 16 ...
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Address 0150 16 0151 16 0152 16 0153 16 0154 16 0155 16 0156 16 0157 ...
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Address 01E0 CAN0 Message Slot Buffer 0 Standard ID0 16 01E1 CAN0 Message Slot Buffer 0 ...
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Address 0210 16 CAN0 Slot Interrupt Mask Register 0211 16 0212 16 0213 16 0214 CAN0 ...
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Address CAN0 Message Slot 10 Control Register / 023A 16 CAN0 Local Mask Register B Extended ...
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Address 0260 CAN1 Message Slot Buffer 0 Standard ID0 16 0261 CAN1 Message Slot Buffer 0 ...
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Address 0290 16 CAN1 Slot Interrupt Mask Register 0291 16 0292 16 0293 16 0294 CAN1 ...
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Address CAN1 Message Slot 10 Control Register / 02BA 16 CAN1 Local Mask Register B Extended ...
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Address 02E0 X/Y Control Register 16 02E1 16 02E2 16 02E3 16 02E4 UART1 Special Mode ...
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Address 0310 16 Timer B3 Register 0311 16 0312 16 Timer B4 Register 0313 16 0314 ...
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Address 0340 Count Start Flag 16 0341 Clock Prescaler Reset Flag 16 0342 One-Shot Start Flag ...
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Address 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 ...
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<144-pin package> Address 03A0 Function Select Register A8 16 03A1 Function Select Register A9 16 03A2 ...
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<144-pin package> Address 03D0 Port P14 Register 16 03D1 Port P15 Register 16 03D2 Port P14 ...
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<100-pin package> Address 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 ...
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<100-pin package> Address 03D0 16 03D1 16 03D2 Set default value to " 03D3 ...
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Reset Hardware reset 1, brown-out detection reset (hardware reset 2), software reset and watchdog timer ...
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CC2 ( CC1 td(P- more 20 or ...
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Table 5.1 Pin States while RESET Pin is Held "L" Pin Name CNV SS P0 Input ...
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When Stop Mode is not Used Vdet4 Vdet3r V CC1 Vdet3 Vdet3s V SS RESET Internal ...
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5.5 Internal Space Figure 5.4 shows CPU register states after reset. Refer to 4. SFR for ...
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Voltage Detection Circuit NOTE The voltage detection circuit in M32C/85T cannot be used. However, the ...
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Watchdog Timer Control Register NOTES: 1. The WDC5 bit ...
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Voltage Detection Register ...
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Low Voltage Detection Interrupt Register NOTES: 1. Set the ...
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6.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to ...
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Low Voltage Detection Circuit CPU VC27 bit Clock VC13 V CC1 + Noise V Rejection - ...
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6.1.1 Limitations on Exiting Stop/Wait Mode The low voltage detection interrupt is generated and the microcomputer ...
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Processor Mode NOTE Use M32C/85T in single-chip mode only. M32C/85T cannot be used in memory ...
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7.2 Setting of Processor Mode The CNV pin state and the PM01 and PM00 bit settings ...
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Processor Mode Register NOTES: 1. Rewrite the ...
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Processor Mode Register NOTES: 1. Rewrite ...
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Figure 7.3 Memory Map in Each Processor Mode Page ...
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Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins ...
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8.1.1 Selecting External Address Bus The number of externally-output address buses, the number of chip-select signals ...
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Table 8.2 Processor Mode and Port Function Single- Processor Chip Mode Mode PM05 to Access CS1 ...
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8.2 Bus Control Signals, required to access external devices, are provided and software wait states are ...
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Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in ...
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8.2.3 Read and Write Signals When using a16-bit data bus, the PM02 bit in the PM0 ...
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8.2.4 Bus Timing Bus cycle for the internal ROM and internal RAM is basically one BCLK ...
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Table 8.5 Software Wait State and Bus Cycle ...
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• Bus Cycle bus cycle = 2 BCLK Address ( ...
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• Bus Cycle BCLK Address ( Data (Read) RD Data (Write) ...
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• Bus Cycle Data (Read) Data (Write) WR, WRL, WRH • Bus Cycle ...
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• Bus Cycle bus cycle = 4 BCLK ( Data ...
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• Bus Cycle Data (Read) Data (Write) WR (WRL) • Bus Cycle 3 ...
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8.2.4.1 Bus Cycle with Recovery Cycle Added The EWCRi06 bit in the EWCRi register (i=0 to ...
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8.2.5 ALE Signal The ALE signal latches an address of the multiplexed bus. Latch an address ...
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(1) Separate Bus with 2 Wait States 1st cycle BCLK RD ( (i=0 to ...
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_________ 8.2.7 HOLD Signal __________ The HOLD signal transfers bus privileges from the CPU to external ...
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Clock Generation Circuit 9.1 Types of the Clock Generation Circuit Four circuits are included to ...
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Figure 9.1 Clock Generation Circuit ...
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System Clock Control Register NOTES: 1. Rewrite the ...
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System Clock Control Register ...
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Main Clock Division Register NOTES: 1. Rewrite the MCD ...
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Oscillation Stop Detection Register NOTES: ...
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Count Source Prescaler Register NOTES: 1. Rewrite the CNT3 ...
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PLL Control Register NOTES: 1. Rewrite ...
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Processor Mode Register NOTES: 1. Rewrite the ...
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9.1.1 Main Clock Main clock oscillation circuit generates the main clock. The main clock becomes clock ...
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9.1.2 Sub Clock Sub clock oscillation circuit generates the sub clock. The sub clock becomes clock ...
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9.1.3 On-Chip Oscillator Clock On-chip oscillator generates the on-chip oscillator clock. The 1-MHz on-chip oscillator clock ...
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"01000 (main clock as CPU clock source) Figure 9.11 Switching Procedure from On-chip Oscillator ...
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9.1.4 PLL Clock The PLL frequency synthesizer generates the PLL clock based on the main clock. ...
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9.2 CPU Clock and BCLK The CPU operating clock is referred to as the CPU clock. ...
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9.3.3 f C32 f is the sub clock divided by 32. f C32 when the sub ...
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9.5 Power Consumption Control Normal operating mode, wait mode and stop mode are provided as the ...
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Switch the CPU clock after the clock to be switched to stabilize. Sub clock oscillation will ...
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9.5.2.3 Pin Status in Wait Mode Table 9.7 lists pin states in wait mode. Table 9.7 ...
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Table 9.8 Interrupts to Exit Wait Mode ...
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9.5.3.1 Entering Stop Mode Stop mode is entered when setting the CM10 bit in the CM10 ...
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9.5.3.2 Exiting Stop Mode Stop mode is exited by the hardware reset, NMI interrupt or peripheral ...
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All oscillation is stopped CM10=1 Stop Mode Interrupt Stop Mode CM10=1 (Note 2) NOTES: 1. See ...
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Figure 9.14 Status Transition ...
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9.6 System Clock Protect Function The system clock protect function prohibits the CPU clock from changing ...
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10. Protection The protection function protects important registers from being easily overwritten when a program runs ...
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11. Interrupts 11.1 Types of Interrupts Figure 11.1 shows types of interrupts. Software (Non-Maskable Interrupt) Interrupt ...
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11.2 Software Interrupts Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable ...
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11.3 Hardware Interrupts Special interrupts and peripheral function interrupts are available as hardware interrupts. 11.3.1 Special ...
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11.4 High-Speed Interrupt The high-speed interrupt executes an interrupt sequence in five cycles and returns from ...
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11.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses FFFFDC tables. Refer to 25.2 ...
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Table 11.2 Relocatable Vector Tables Interrupt Generated by (2) BRK Instruction Reserved Space DMA0 DMA1 DMA2 ...
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Table 11.2 Relocatable Vector Tables (Continued) Interrupt Generated by Bus Conflict Detect, Start Condition Detect, +156 ...
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11.6 Interrupt Request Acknowledgement Software interrupts and special interrupts occur when conditions to generate an interrupt ...
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Interrupt Control Register NOTES: 1. The BCN0IC register shares ...
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Interrupt Control Register NOTES: 1. When a 16-bit data ...
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Exit Priority Register NOTES: 1. The microcomputer exits stop ...
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11.6.3 Interrupt Sequence The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine ...
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11.6.4 Interrupt Response Time Figure 11.6 shows an interrupt response time. Interrupt response time is the ...
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Table 11.4 Interrupt Sequence Execution Time Interrupt Peripheral Function INT Instruction _______ NMI Watchdog Timer Undefined ...
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11.6.6 Saving a Register In the interrupt sequence, the FLG register and PC are saved to ...
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11.6.8 Interrupt Priority If two or more interrupt requests are sampled at the same sampling points ...
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High Each Interrupt Priority Level DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer ...
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______ 11.7 INT Interrupt External input generates the INTi interrupt ( 5). The ...
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______ (1) 11.8 NMI Interrupt ______ The NMI interrupt occurs when a signal applied to the ...
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11.10 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is ...
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11.11 Intelligent I/O Interrupt and CAN Interrupt The intelligent I/O interrupt and CAN interrupt are assigned ...
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The CANjk (j k interrupt and CAN1 wake-up interrupt are provided as ...
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Interrupt Request Register NOTES: 1. See table below ...
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Interrupt Enable Register NOTES: 1. See table below ...
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12. Watchdog Timer The watchdog timer monitors the program executions and detects defective program. It allows ...
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Watchdog Timer Control Register NOTES: 1. The WDC5 ...
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System Clock Control Register NOTES: 1. Rewrite the ...
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12.1 Count Source Protection Mode In count source protection mode, the on-chip oscillator clock is used ...
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13. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to ...
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DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to ...
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DMAi Request Source Select Register NOTES: 1. Change the ...
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Table 13.2 DMiSL Register ( Function Setting Value ...
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DMA Mode Register NOTES: 1. Use the LDC ...
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DMAi Transfer Count Register b15 b8 b7 NOTES: 1. When the DCTi register is set to ...
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DMAi Memory Address Register b23 b16 b15 NOTES: 1. When the RWk bit (k ...
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13.1 Transfer Cycle Transfer cycle contains a bus cycle to read data from a memory or ...
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(1) When 8-bit data is transferred or when 16-bit data is transferred with a 16-bit data ...
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13.2 DMAC Transfer Cycle The number of DMAC transfer cycle can be calculated as follows. Any ...
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When DMA transfer request signals by external source are applied to INT0 and INT1 simultaneously and ...
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14. DMAC II DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which transfers ...
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Exit Priority Register NOTES: 1. The microcomputer exits stop ...
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14.1.2 DMAC II Index The DMAC II index is a data table which comprises 8 to ...
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Table 14.2 DMAC II Index Configuration in Transfer Mode Memory-to-Memory Transfer Transfer Data /Immediate Data Transfer ...
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14.1.3 Interrupt Control Register for the Peripheral Function For the peripheral function interrupt activating DMAC II, ...
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14.3.2 Immediate Data Transfer DMAC II transfers immediate data to any memory location. A fixed or ...
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14.6 Chained Transfer The CHAIN bit in MOD selects the chained transfer. The following process initiates ...
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14.8 Execution Time DMAC II execution cycle is calculated by the following equations: Multiple transfers: t ...
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15. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have ...
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C32 TCK1 to TCK0 TB0 ...
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15.1 Timer A Figure 15.3 shows a block diagram of the timer A. Figures 15.4 to ...
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Timer Ai Register b15 ...
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Timer Ai Mode Register Count Start Flag b7 ...
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(1) Up/Down Flag NOTES: 1. Use the MOV instruction ...
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Trigger Select Register NOTES: 1. Overflow or underflow Count ...
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Table 15.1 Pin Settings for Output from TAi Pin PS1, PS2 Registers OUT (1) P7 /TA0 ...
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15.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table ...
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Timer Ai Mode Register NOTES ...
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15.1.2 Event Counter Mode In event counter mode, the timer counts how many external signals are ...
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Table 15.5 Event Counter Mode Specifications (When Processing Two-phase Pulse Signal on Timer A2, A3 and ...
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Timer Ai Mode Register NOTES: 1. ...
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15.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing Z-phase input resets the timer counter when processing ...
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15.1.3 One-Shot Timer Mode In one-shot timer mode, the timer operates only once for each trigger ...
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Timer Ai Mode Register NOTES: 1. ...
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15.1.4 Pulse Width Modulation Mode In pulse width modulation mode, the timer outputs pulse of desired ...
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Timer Ai Mode Register NOTES: 1. MR1 ...
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When the reload register is set to "0003 of a signal applied to the TAi Count ...
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15.2 Timer B Figure 15.16 shows a block diagram of the timer B. Figures 15.17 to ...
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Timer Bi Mode Register NOTES: 1. Only MR2 bits ...
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Timer B3, B4,B5 Count Start Flag Figure 15.19 TBSR ...
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15.2.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table ...
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15.2.2 Event Counter Mode In event counter mode, the timer counts how many external signals are ...