M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 108

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
Figure 9.4 MCD Register
0
C
1
9
8 /
0 .
B
0
3
5
0
G
3
J
7
u
o r
0 -
Main Clock Division Register
. l
b7
NOTES:
u
0
1
p
, 1
0
b6
1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the microcomputer enters stop mode or low-power consumption mode, the MCD4 to MCD0 bits
3. Bit combinations cannot be set not listed above.
4. Access CAN-associated register addresses after setting the MCD4 to MCD0 bits are set to "10010
3
(
2
M
when the PM24 bit in the PM2 register is set to "0" (clock selected by the CM07 bit).
are set to "01000
The MCD4 to MCD0 bits are not set to "01000
(X
b5
0
3
IN
0
2
5
-X
b4
C
OUT
8 /
b3
Page 83
, 5
stopped) in on-chip oscillator mode.
b2
M
3
b1
2
2
C
".
b0
f o
8 /
4
5
(b7 - b5)
Symbol
MCD0
MCD1
MCD2
MCD3
MCD4
9
) T
4
Bit
Symbol
MCD
Main Clock Division
Select Bit
Reserved Bit
(1)
Bit Name
(2, 4)
Address
000C
2
" even if the CM05 bit in the CM0 register is set to "1"
16
b4 b3 b2 b1 b0
1 0 0 1 0 : Divide-by-1(no division)
0 0 0 1 0 : Divide-by-2 mode
0 0 0 1 1 : Divide-by-3 mode
0 0 1 0 0 : Divide-by-4 mode
0 0 1 1 0 : Divide-by-6 mode
0 1 0 0 0 : Divide-by-8 mode
0 1 0 1 0 : Divide-by-10 mode
0 1 1 0 0 : Divide-by-12 mode
0 1 1 1 0 : Divide-by-14 mode
0 0 0 0 0 : Divide-by-16 mode
When read,
its content is indeterminate
mode
After Reset
XXX0 1000
Function
2
9. Clock Generation Circuit
(Note 3)
RW
RW
RW
RW
RW
RW
RO
2
",