M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 268

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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R
M
e
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3
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2
Figure 17.32 SIM Interface Format
0
17.7.2 Format
C
1
9
0 .
8 /
B
0
17.7.2.1 Direct Format
17.7.2.2 Inverse Format
3
5
0
3
G
J
parity), the UFORM bit in the UiC0 register to "0" (LSB first) and the UiLCH bit in the UiC1 register to
"0" (not inversed). When data are transmitted, data set in the UiTB register are transmitted with the
even-numbered parity, starting from D
UiRB register, starting from D
UiLCH bit to "1" (inversed). When data are transmitted, values set in the UiTB register are logically
inversed and are transmitted with the odd-numbered parity, starting from D
ceived, received data are logically inversed to be stored in the UiRB register, starting from D
odd-numbered parity determines whether a parity error occurs.
7
Set the PRYE bit to "1", the PRY bit to "0" (odd parity), the UFORM bit to "1" (MSB first) and the
u
Set the PRYE bit in the UiMR register (i=0 to 4) to "1" (parity enabled), the PRY bit to "1" (even
o r
0 -
. l
u
0
1
, 1
0
p
3
(
2
M
0
Transfer Clock
Transfer Clock
0
3
(1) Direct Format
5
2
(2) Inverse Format
C
8 /
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TxD
TxD
i=0 to 4
M
i
i
3
2
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
C
f o
8 /
4
5
9
) T
4
0
. The even-numbered parity determines whether a parity error occurs.
D
D
0
7
0.
D
D
1
6
When data are received, received data are stored in the
D
D
2
5
D
D
3
4
D
D
3
4
D
D
2
5
D
D
6
1
D
D
7
0
17. Serial I/O (Special Function)
P : Even parity
P : Odd parity
P
P
7
. When data are re-
7
. The